ADF7025BCPZ-RL7 Analog Devices Inc, ADF7025BCPZ-RL7 Datasheet
ADF7025BCPZ-RL7
Specifications of ADF7025BCPZ-RL7
Related parts for ADF7025BCPZ-RL7
ADF7025BCPZ-RL7 Summary of contents
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FEATURES Low power, zero-IF RF transceiver Frequency bands 431 MHz to 464 MHz 862 MHz to 870 MHz 902 MHz to 928 MHz Data rates supported 9.6 kbps to 384 kbps, FSK 2 3.6 V power supply Programmable ...
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ADF7025 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications..................................................................................... 4 Timing Characteristics..................................................................... 7 Timing Diagrams.......................................................................... 7 Absolute Maximum Ratings............................................................ 9 ESD Caution.................................................................................. 9 Pin Configuration and ...
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GENERAL DESCRIPTION The ADF7025 is a low power, highly integrated FSK transceiver designed for operation in the license–free ISM bands of 433 MHz, 863 MHz to 870 MHz, and 902 MHz to 928 MHz. The ADF7025 can be ...
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ADF7025 SPECIFICATIONS 3.6 V, GND = All measurements are performed using the EVAL-ADF7025DB1 using PN9 data sequence, unless otherwise noted. Table 1. Parameter RF CHARACTERISTICS Frequency Ranges (Direct ...
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Parameter CHANNEL FILTERING Adjacent Channel Rejection (Offset = ±1 × LP Filter BW Setting) Second Adjacent Channel Rejection (Offset = ±2 × LP Filter BW Setting) Third Adjacent Channel Rejection (Offset = ±3 × LP Filter BW Setting) Co-Channel Rejection ...
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ADF7025 Parameter LOGIC INPUTS Input High Voltage, V INH Input Low Voltage, V INL Input Current INH INL Input Capacitance Control Clock Input LOGIC OUTPUTS Output High Voltage Output Low Voltage CLK ...
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TIMING CHARACTERISTICS ± 10%; VGND = 25°C, unless otherwise noted Table 2. 1 Parameter Limit MIN t < < < ...
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ADF7025 ±1 × DATA RATE/32 RxCLK RxDATA 1/DATA RATE DATA Figure 4. RxData/RxCLK Timing Diagram Rev Page ...
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ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter GND DD Analog I/O Voltage to GND Digital I/O Voltage to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature ...
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ADF7025 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RFGND Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 VCOIN The tuning voltage on this pin determines the output frequency of the voltage-controlled oscillator (VCO). The higher the tuning voltage, the higher ...
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Pin No. Mnemonic Description 29 GND2 Ground for Digital Section. 30 ADCIN Analog-to-Digital Converter Input. The internal 7-bit ADC can be accessed through this pin. Full scale 1.9 V. Readback is made using the SREAD pin. ...
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ADF7025 TYPICAL PERFORMANCE CHARACTERISTICS CARRIER POWER 6.11dBm ATTEN 2.00dB MKR1 REF –60dBc/Hz 10.00dB/ 1 100Hz FREQUENCY OFFSET Figure 6. Phase Noise Response at 915 MHz, V REF 10dBm NORM LOG 10dB/ ATTEN 20dB 1R 1 CENTER 915.00MHz VBW 10kHz #RES ...
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ACTUAL INPUT LEVEL –20 –40 RSSI READBACK LEVEL –60 –80 –100 –120 –120 –100 –80 –60 –40 –20 RF I/P (dB) Figure 12. Digital RSSI Readback – –12 –6 ...
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ADF7025 –60 = CORRELATOR –65 = LINEAR –70 –75 –80 – ±300kHz ±450kHz –90 –95 –100 –105 –110 0 50 100 150 200 250 300 350 400 450 500 550 600 DEVIATION FREQUENCY (kHz) ...
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FREQUENCY SYNTHESIZER REFERENCE INPUT SECTION The on-board crystal oscillator circuitry (see Figure 19) can use an inexpensive quartz crystal as the PLL reference. The oscillator circuit is enabled by setting R1_DB12 high enabled by default on power-up and ...
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ADF7025 Analog Lock Detect This N-channel open-drain lock detect should be operated with an external pull-up resistor of 10 kΩ nominal. When a lock has been detected, this output is high with narrow low-going pulses. Voltage Regulators The ADF7025 contains ...
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VCO Bias Current VCO bias current can be adjusted using Bit R1_DB19 to Bit R1_DB16. To ensure VCO oscillation under all conditions, the minimum bias current setting is Setting 12 (0xC). 431 MHz to 464 MHz Operation For operation in ...
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ADF7025 TRANSMITTER RF OUTPUT STAGE The PA of the ADF7025 is based on a single-ended, controlled current, open-drain amplifier that has been designed to deliver dBm into a 50 Ω load at a maximum frequency of 928 ...
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RECEIVER RF FRONT END The ADF7025 is based on a fully integrated, zero-IF receiver architecture. The zero-IF architecture minimizes power consumption and the external component count while avoiding the need for image rejection. Figure 27 shows the structure of the ...
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ADF7025 RSSI/AGC The RSSI is implemented as a successive compression log amp following the baseband channel filtering. The log amp achieves ±3 dB log linearity. It also doubles as a limiter to convert the signal-to-digital levels for the FSK demodulator. ...
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Postdemodulator Filter A second-order, digital low-pass filter removes excess noise from the demodulated bit stream at the output of the discriminator. The bandwidth of this postdemodulator filter is programmable and must be optimized for the user’s data rate. If the ...
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ADF7025 LINEAR FSK DEMODULATOR A block diagram of the linear FSK demodulator is shown in Figure 30. MUX 1 ADC RSSI OUTPUT 7 LEVEL I LIMITER FREQ Q 0Hz LINEAR DISCRIMINATOR DB(6:15) Figure 30. Block Diagram of Linear FSK Demodulator ...
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APPLICATIONS SECTION LNA/PA MATCHING The ADF7025 exhibits optimum performance in terms of sensitivity, transmit power, and current consumption only if its RF input and output ports are properly matched to the antenna impedance. For cost-sensitive applications, the ADF7025 is equipped ...
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ADF7025 The procedure typically requires several iterations until an acceptable compromise is reached. The successful implementation of a combined LNA/PA matching network for the ADF7025 is critically dependent on the availability of an accurate electrical model for the PC board. ...
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TO 22mA 14mA XTAL T 0 3.65mA 2.0mA REG. READY WR0 WR1 Table 8. Power-Up Sequence Description Parameter Value Description/Notes XTAL starts power-up after CE is brought high. This typically ...
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ADF7025 15mA TO 30mA 14mA 3.65mA 2.0mA REG. READY WR0 WR1 XTAL + VCO TxDATA WR2 Figure 37. Tx Programming Sequence and Timing Diagram Rev. A ...
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SERIAL INTERFACE The serial interface allows the user to program the eleven 32-bit registers using a 3-wire interface (SCLK, SDATA, and SLE). It consists of a level shifter, a 32-bit shift register, and 11 latches. Signals should be CMOS-compatible. The ...
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ADF7025 REGISTERS REGISTER 0—N REGISTER MUXOUT 8-BIT INTEGER-N TRANSMIT/ TR1 RECEIVE 0 TRANSMIT 1 RECEIVE PLE1 PLL ENABLE 0 PLL OFF 1 PLL MUXOUT REGULATOR READY (DEFAULT ...
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REGISTER 1—OSCILLATOR/FILTER REGISTER FREQUENCY VA2 VA1 OF OPERATION 0 0 850–920 0 1 860–930 1 0 870–940 1 1 880–950 VB4 VB3 FILTER IR2 IR1 BANDWIDTH 0 0 600kHz 0 1 900kHz ...
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ADF7025 REGISTER 2—TRANSMIT MODULATION REGISTER GFSK MOD PA BIAS CONTROL IC2 IC1 MC3 MC2 MC1 DI1 0 TxDATA 1 TxDATA PA2 PA1 PA BIAS 0 0 5µ 7µ 9µ ...
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REGISTER 3—RECEIVER CLOCK REGISTER SEQUENCER CLOCK DIVIDE SK8 SK7 ... SK3 ... ... ... . . . ... ... Register 3—Receiver Clock Register Comments • Baseband offset clock ...
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ADF7025 REGISTER 4—DEMODULATOR SETUP REGISTER DEMOD MODE LM2 LM1 DL8 DEMOD LOCK/SYNC WORD MATCH SERIAL PORT CONTROL – FREE RUNNING SERIAL PORT CONTROL – LOCK THRESHOLD SYNC WORD ...
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REGISTER 5—SYNC BYTE REGISTER Register 5—Sync Byte Register Comments • Sync byte detect is enabled by programming Bits R4_DB [25:23] to 010 or 011. • This register allows a 24-bit sync byte sequence to be stored internally. If the sync ...
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ADF7025 REGISTER 6—CORRELATOR/DEMODULATOR REGISTER Rx IF FILTER DIVIDER RESET CA1 DEMOD 0 RESET 1 CDR ML1 MIXER LINEARITY RESET 0 DEFAULT 1 HIGH RxDATA RI1 INVERT 0 RxDATA 1 RxDATA FC9 . FC6 FC5 FC4 ...
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REGISTER 7—READBACK SETUP REGISTER RB3 READBACK 0 DISABLED 1 ENABLED Register 7—Readback Setup Register Comments • Readback of the measured RSSI value is valid only in Rx mode. Readback of the battery voltage, the temperature sensor, and the voltage at ...
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ADF7025 REGISTER 8—POWER-DOWN TEST REGISTER DB15 DB14 DB13 DB12 PD7 SW1 PD7 PA (Rx MODE OFF SW1 Tx/Rx SWITCH 0 DEFAULT (ON) 1 OFF LR2 LR1 RSSI MODE X 0 RSSI OFF X 1 RSSI ...
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REGISTER 9—AGC REGISTER DIGITAL FILTER TEST IQ GAIN FI1 FILTER CURRENT 0 LOW 1 HIGH FG2 FG1 FILTER GAIN INVALID Register 9—AGC Register Comments • The recommended AGC threshold ...
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ADF7025 REGISTER 10—AGC 2 REGISTER I/Q PHASE ADJUST SIQ2 SELECT IQ 0 PHASE TO I CHANNEL 1 PHASE TO Q CHANNEL Register 10—AGC 2 Register Comments • Register 10 is not used under normal operating conditions. • If adjusting AGC ...
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REGISTER 12—TEST REGISTER ANALOG TEST MUX P PRESCALER 0 4/5 (DEFAULT) 1 8/9 CS1 CAL SOURCE 0 INTERNAL 1 SERIAL IF BW CAL Using the Test DAC on the ADF7025 to Implement Analog FM DEMOD and Measuring SNR The test ...
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ADF7025 REGISTER 13—OFFSET REMOVAL AND SIGNAL GAIN REGISTER TEST DAC GAIN TEST DAC OFFSET REMOVAL Register 13—Offset Removal and Signal Gain Register Comments Because the linear demodulator output is proportional to frequency, it usually consists of an offset combined with ...
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... MAX 0.85 0.80 SEATING PLANE ORDERING GUIDE Model Temperature Range 1 ADF7025BCPZ −40°C to +85°C 1 ADF7025BCPZ-RL −40°C to +85°C 1 ADF7025BCPZ-RL7 −40°C to +85°C EVAL-ADF70XXMB EVAL-ADF70XXMB2 EVAL-ADF7025DB1 Pb-free part. 7.00 BSC SQ 0.60 MAX 37 36 TOP 6.75 VIEW BSC SQ ...
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ADF7025 NOTES Rev Page ...
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NOTES Rev Page ADF7025 ...
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ADF7025 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05542-0-2/06(A) Rev Page ...