ADF7025BCPZ-RL7 Analog Devices Inc, ADF7025BCPZ-RL7 Datasheet - Page 25

• Manufacturer Part Number: ADF7025BCPZ-RL7
• Description: IC,RF Modulator/Demodulator,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of ADF7025BCPZ-RL7

• Frequency: 431MHz ~ 464MHz, 862MHz ~ 870MHz and 902MHz ~ 928MHz
• Data Rate - Maximum: 384kbps
• Modulation Or Protocol: FSK
• Applications: Keyless Entery, Home Automation, Wireless Audio/Video
• Power - Output: -20dBm ~ 13dBm
• Sensitivity: -104dBm
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Receiving: 19mA
• Current - Transmitting: 28mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LFCSP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Modulation Type: FSK
• Product Depth (mm): 7mm
• Product Length (mm): 7mm
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF70XXEKZ1 - KIT DEV ADF702X FOR BF533EZKITEVAL-ADF7025DBZ1 - BOARD EVAL ADF7025 902-928MHZ
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Table 8. Power-Up Sequence Description
Parameter
T
T
T
T
T
T
T
T
0
1
2
6
4
8
9
11
, T
, T
3
7
, T
5
,
19mA TO
3.65mA
2.0mA
22mA
14mA
Value
2 ms
10 µs
32 × 1/SPI_CLK
1 ms
150 µs
5 × bit_period
Packet length
READY
REG.
T
1
WR0
T
2
WR1
T
3
Description/Notes
XTAL starts power-up after CE is brought high. This typically depends on the XTAL
type and the load capacitance specified.
Time for regulator to power up. The serial interface can be written to after this time.
Time to write to a single register. Maximum SPI_CLK is 25 MHz.
The VCO can power-up in parallel with the XTAL. This depends on the CVCO
capacitance value used. A value of 22 nF is recommended as a trade-off
between phase noise performance and power-up time.
This depends on the number of gain changes the AGC loop needs to cycle through
and AGC settings programmed. This is described in more detail in the AGC Information
section.
This is the time for the clock and data recovery circuit to settle. This typically requires
5-bit transitions to acquire sync and is usually covered by the preamble.
Number of bits in payload by the bit period.
XTAL
T
0
VCO
T
4
Figure 36. Rx Programming Sequence and Timing Diagram
WR3
T
5
WR4
T
6
WR6
T
T
7
ON
Rev. A | Page 25 of 44
AGC/
RSSI
T
8
CDR
T
9
Rx
T
DATA
11
T
OFF
TIME
Signal to
Monitor
CLKOUT
CVCO pin
Analog RSSI
on TEST_A pin
MUXOUT
ADF7025