ADF7025BCPZ-RL7 Analog Devices Inc, ADF7025BCPZ-RL7 Datasheet - Page 31

• Manufacturer Part Number: ADF7025BCPZ-RL7
• Description: IC,RF Modulator/Demodulator,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of ADF7025BCPZ-RL7

• Frequency: 431MHz ~ 464MHz, 862MHz ~ 870MHz and 902MHz ~ 928MHz
• Data Rate - Maximum: 384kbps
• Modulation Or Protocol: FSK
• Applications: Keyless Entery, Home Automation, Wireless Audio/Video
• Power - Output: -20dBm ~ 13dBm
• Sensitivity: -104dBm
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Receiving: 19mA
• Current - Transmitting: 28mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LFCSP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Modulation Type: FSK
• Product Depth (mm): 7mm
• Product Length (mm): 7mm
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF70XXEKZ1 - KIT DEV ADF702X FOR BF533EZKITEVAL-ADF7025DBZ1 - BOARD EVAL ADF7025 902-928MHZ
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant

REGISTER 3—RECEIVER CLOCK REGISTER
Register 3—Receiver Clock Register Comments
• Baseband offset clock frequency (BBOS_CLK) must be greater than 1 MHz and less than 2 MHz, where:
• The demodulator clock (DEMOD_CLK) must be < 12 MHz, where:
• Data/clock recovery frequency (CDR_CLK) should be within 2% of (32 × data rate), where:
• The sequencer clock (SEQ_CLK) supplies the clock to the digital receive block. It should be close to 100 kHz.
Note that this can affect the choice of XTAL, depending on the desired data rate.
CDR
SEQ
BBOS
DEMOD
_
_
_
CLK
CLK
CLK
_
CLK
=
=
=
SEQ
CDR
BBOS
=
DEMOD
_
DEMOD
_
CLK
CLK
XTAL
_
SK8
0
0
.
1
1
CLK
XTAL
SEQUENCER CLOCK DIVIDE
_
_
_
DIVIDE
SK7
0
0
.
1
1
_
DIVIDE
_
CLK
XTAL
CLK
DIVIDE
...
...
...
...
...
...
_
DIVIDE
SK3
0
0
.
1
1
SK2
0
1
.
1
1
FS8
0
0
.
1
1
SK1
1
0
.
0
1
Figure 42. Register 3—Receiver Clock Register
FS7
0
0
.
1
1
SEQ_CLK_DIVIDE
1
2
.
254
255
...
...
...
...
...
...
CDR CLOCK DIVIDE
Rev. A | Page 31 of 44
FS3
0
0
.
1
1
FS2
0
1
.
1
1
FS1
1
0
.
0
1
CDR_CLK_DIVIDE
1
2
.
254
255
OK2
0
0
1
1
OK1
0
1
0
1
BK2
0
0
1
DEMOD_CLK_DIVIDE
4
1
2
3
BK1
0
1
x
BBOS_CLK_DIVIDE
4
8
16
ADDRESS
BITS
ADF7025