ADF7025BCPZ-RL7 Analog Devices Inc, ADF7025BCPZ-RL7 Datasheet - Page 34

• Manufacturer Part Number: ADF7025BCPZ-RL7
• Description: IC,RF Modulator/Demodulator,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of ADF7025BCPZ-RL7

• Frequency: 431MHz ~ 464MHz, 862MHz ~ 870MHz and 902MHz ~ 928MHz
• Data Rate - Maximum: 384kbps
• Modulation Or Protocol: FSK
• Applications: Keyless Entery, Home Automation, Wireless Audio/Video
• Power - Output: -20dBm ~ 13dBm
• Sensitivity: -104dBm
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Receiving: 19mA
• Current - Transmitting: 28mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LFCSP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Modulation Type: FSK
• Product Depth (mm): 7mm
• Product Length (mm): 7mm
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF70XXEKZ1 - KIT DEV ADF702X FOR BF533EZKITEVAL-ADF7025DBZ1 - BOARD EVAL ADF7025 902-928MHZ
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant

ADF7025
REGISTER 6—CORRELATOR/DEMODULATOR REGISTER
Register 6—Correlator/Demodulator Register Comments
• See the FSK Correlator/Demodulator section for an example of how to determine register settings.
• Nonadherence to correlator programming guidelines results in poor sensitivity.
• The filter clock is used to calibrate the LP filter. The filter clock divide ratio should be adjusted so that the frequency is 50 kHz.
• The filter should be calibrated only when the crystal oscillator is settled. The filter calibration is initiated every time Bit R6_DB19
• Discriminator_BW = DEMOD_CLK/(4 × DEVIATION_Frequency). See the FSK Correlator/Demodulator section.
• When LNA Mode = 1 (reduced gain mode), the Rx is prevented from selecting the highest LNA gain setting. This can be used when
The formula is XTAL/FILTER_CLOCK_DIVIDE.
is set high.
Maximum value = 600.
linearity is a concern. See the Readback Format section for details of the different Rx modes.
RESET
CDR
RESET
Rx
DEMOD
RESET
RI1
0
1
FC9
0
0
.
.
.
.
1
RxDATA
INVERT
RxDATA
RxDATA
.
.
.
.
.
.
.
.
FC6
0
0
.
.
.
.
1
IF FILTER DIVIDER
FC5
0
0
.
.
.
.
1
ML1
0
1
FC4
0
0
.
.
.
.
1
CA1
0
1
MIXER LINEARITY
DEFAULT
HIGH
FC3
0
0
.
.
.
.
1
FILTER CAL
NO CAL
CALIBRATE
FC2
0
1
.
.
.
.
1
Figure 45. Register 6—Correlator/Demodulator Register
FC1
1
0
.
.
.
.
1
FILTER CLOCK
DIVIDE RATIO
1
2
.
.
.
.
511
LI2
0
LI1
0
Rev. A | Page 34 of 44
LNA BIAS
800µA (DEFAULT)
DP1
0
1
LG1
0
1
DOT PRODUCT
CROSS PRODUCT
INVALID
LNA MODE
DEFAULT
REDUCED GAIN
DISCRIMINATOR BW
ADDRESS
BITS