ADSP-21065LKSZ-264 Analog Devices Inc, ADSP-21065LKSZ-264 Datasheet - Page 35

• Manufacturer Part Number: ADSP-21065LKSZ-264
• Description: ADSP-21065L 66MHz
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21065LKSZ-264

• Interface: Host Interface, Serial Port
• Clock Rate: 60MHz
• Non-volatile Memory: External
• On-chip Ram: 64kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

JTAG Test Access Port and Emulation
Parameter
Timing Requirements:
t
t
t
t
t
t
Switching Characteristics:
t
t
NOTES
1
2
REV. C
System Inputs = DATA
System Outputs = DATA
TCK
STAP
HTAP
SSYS
HSYS
TRSTW
DTDO
DSYS
TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, BSEL, BMS, CLKIN, RESET, SDCLK
TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, BMS, SDCLK0, SDCLK1, DQM, SDA10, RAS, CAS, SDWE, SDCKE, BM, XTAL.
TCK Period
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK Low
System Inputs Hold After TCK Low
TRST Pulsewidth
TDO Delay from TCK Low
System Outputs Delay After TCK Low
31-0
31-0
OUTPUTS
, ADDR
SYSTEM
SYSTEM
, ADDR
INPUTS
TMS
TDO
TCK
TDI
23-0
23-0
, RD, WR, ACK, SBTS, SW, HBR, HBG, CS, DMAR
, MS
3-0
, RD, WR, ACK, SW, HBG, REDY, DMAG1
Figure 23. JTAG Test Access Port and Emulation
t
DTDO
1
t
t
STAP
DSYS
1
2
–35–
t
t
TCK
HTAP
1
,
, DMAR
Min
t
3.0
3.0
7.0
12.0
4 t
DMAG2, BR
CK
0
, RAS, CAS, SDWE, SDCKE, PWM_EVENTx.
CK
2
t
, BR
SSYS
2-1
2-1
, CPA, FLAG
, ID
1-0
, IRQ
2-0
t
HSYS
11-0
, FLAG
, PWM_EVENTx, DT0x, DT1x,
Max
15.0
11.0
11-0
ADSP-21065L
, DR0x, DR1x, TCLK0,
Unit
ns
ns
ns
ns
ns
ns
ns
ns