ADSP-21065L 60 Mhz

ADSP-21065LCSZ-240

Manufacturer Part NumberADSP-21065LCSZ-240
DescriptionADSP-21065L 60 Mhz
ManufacturerAnalog Devices Inc
SeriesSHARC®
TypeFixed/Floating Point
ADSP-21065LCSZ-240 datasheet
 


Specifications of ADSP-21065LCSZ-240

InterfaceHost Interface, Serial PortClock Rate60MHz
Non-volatile MemoryExternalOn-chip Ram64kB
Voltage - I/o3.30VVoltage - Core3.30V
Operating Temperature-40°C ~ 100°CMounting TypeSurface Mount
Package / Case208-MQFP, 208-PQFPDevice Core Size32b
ArchitectureEnhanced HarvardFormatFloating Point
Clock Freq (max)60MHzMips60
Device Input Clock Speed60MHzRam Size68KB
Operating Supply Voltage (typ)3.3VOperating Supply Voltage (min)3.13V
Operating Supply Voltage (max)3.6VOperating Temp Range-40C to 100C
Operating Temperature ClassificationIndustrialMountingSurface Mount
Pin Count208Package TypeMQFP
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther namesADS-P21065LCSZ240
ADS-P21065LCSZ240
1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
10
Page 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Page 1/44

Download datasheet (584Kb)Embed
Next
a
SUMMARY
High Performance Signal Computer for Communica-
tions, Audio, Automotive, Instrumentation and
Industrial Applications
Super Harvard Architecture Computer (SHARC
Four Independent Buses for Dual Data, Instruction,
and I/O Fetch on a Single Cycle
32-Bit Fixed-Point Arithmetic; 32-Bit and 40-Bit Floating-
Point Arithmetic
544 Kbits On-Chip SRAM Memory and Integrated I/O
Peripheral
2
I
S Support, for Eight Simultaneous Receive and Trans-
mit Channels
KEY FEATURES
66 MIPS, 198 MFLOPS Peak, 132 MFLOPS Sustained
Performance
User-Configurable 544 Kbits On-Chip SRAM Memory
Two External Port, DMA Channels and Eight Serial
Port, DMA Channels
CORE PROCESSOR
DAG1
DAG2
8
4
32
8
4
24
PM ADDRESS BUS
24
DM ADDRESS BUS
32
PM DATA BUS
48
BUS
CONNECT
40
DM DATA BUS
(PX)
DATA
REGISTER
FILE
16
40 BIT
BARREL
MULTIPLIER
SHIFTER
SHARC is a registered trademark of Analog Devices, Inc.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
SDRAM Controller for Glueless Interface to Low Cost
External Memory (@ 66 MHz)
64M Words External Address Range
12 Programmable I/O Pins and Two Timers with Event
®
)
Capture Options
Code-Compatible with ADSP-2106x Family
208-Lead MQFP or 196-Ball Mini-BGA Package
3.3 Volt Operation
Flexible Data Formats and 40-Bit Extended Precision
32-Bit Single-Precision and 40-Bit Extended-Precision IEEE
Floating-Point Data Formats
32-Bit Fixed-Point Data Format, Integer and Fractional,
with Dual 80-Bit Accumulators
Parallel Computations
Single-Cycle Multiply and ALU Operations in Parallel with
Dual Memory Read/Writes and Instruction Fetch
Multiply with Add and Subtract for Accelerated FFT But-
terfly Computation
1024-Point Complex FFT Benchmark: 0.274 ms (18,221
Cycles)
DUAL-PORTED SRAM
INSTRUCTION
TWO INDEPENDENT
CACHE
DUAL-PORTED BLOCKS
32
48 BIT
PROCESSOR PORT
ADDR
DATA
ADDR
PROGRAM
SEQUENCER
(MEMORY MAPPED)
ALU
STATUS, TIMER
DATA BUFFERS
Figure 1. Functional Block Diagram
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
DSP Microcomputer
ADSP-21065L
JTAG
TEST &
EMULATION
I/O PORT
DATA
ADDR
ADDR
DATA
DATA
EXTERNAL
PORT
SDRAM
IOD
IOA
INTERFACE
48
17
ADDR BUS
MUX
MULTIPROCESSOR
INTERFACE
DATA BUS
MUX
HOST PORT
4
DMA
IOP
CONTROLLER
REGISTERS
(2 Rx, 2Tx)
SPORT 0
CONTROL,
&
(2 Rx, 2Tx)
SPORT 1
I/O PROCESSOR
© 2003 Analog Devices, Inc. All rights reserved.
7
24
32
2
(I
S)
2
(I
S)
www.analog.com

ADSP-21065LCSZ-240 Summary of contents

  • Page 1

    ... Words External Address Range 12 Programmable I/O Pins and Two Timers with Event ® ) Capture Options Code-Compatible with ADSP-2106x Family 208-Lead MQFP or 196-Ball Mini-BGA Package 3.3 Volt Operation Flexible Data Formats and 40-Bit Extended Precision 32-Bit Single-Precision and 40-Bit Extended-Precision IEEE ...

  • Page 2

    ... Efficient Interface to 8-, 16-, and 32-Bit Microprocessors Host Can Directly Read/Write ADSP-21065L IOP Registers Multiprocessing Distributed On-Chip Bus Arbitration for Glueless, Parallel Bus Connect Between Two ADSP-21065Ls Plus Host 132 Mbytes/s Transfer Rate Over Parallel Bus Serial Ports Independent Transmit and Receive Functions ...

  • Page 3

    ... DSP in the industry—they are also the only DSP in the industry that offer both fixed and floating-point capabilities, without compromising precision or performance. The ADSP-21065L is fabricated in a high speed, low power CMOS process, 0.35 mm technology. With its on-chip instruc- tion cache, the processor can execute every instruction in a single cycle ...

  • Page 4

    ... I/O, all in a single cycle (see Figure 4 for the ADSP-21065L Memory Map). On the ADSP-21065L, the memory can be configured as a maximum of 16K words of 32-bit data, 34K words for 16-bit data, 10K words of 48-bit instructions (and 40-bit data) or combinations of different word sizes up to 544 Kbits ...

  • Page 5

    ... Maximum throughput for interprocessor data transfer is 132 Mbytes/sec over the external port. REV. C DEVELOPMENT TOOLS The ADSP-21065L is supported with a complete set of software and hardware development tools, including the EZ-ICE Circuit Emulator and development software. The same EZ-ICE hardware that you use for the ADSP-21060/ ADSP-21062 also fully emulates the ADSP-21065L ...

  • Page 6

    ... ADSP-21065L 10 CLOCK RESET 01 ADSP-21065L #2 CLKIN ADDR 23-0 DATA 31-0 RESET ID 1-0 CONTROL SPORT0 CPA BR SPORT1 ADSP-21065L #1 CS CLKIN ADDR DATA RESET ID ADDR 1-0 23-0 PROCESSOR DATA 31-0 (OPTIONAL) SPORT0 ADDR ACK DATA MS 3-0 BMS ADDR SPORT1 SBTS SW DATA CS HBR CS CONTROL HBG ...

  • Page 7

    ... PIN DESCRIPTIONS ADSP-21065L pin definitions are listed below. Inputs identified as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as asynchronous (A) can be asserted asynchronously to CLKIN (or to TCK for TRST). Unused inputs should be tied or pulled to VDD or GND, except for ADDR internal pull-up or pull-down resistors (CPA, ACK, DTxX, DRxX, TCLKx, RCLKx, TMS, and TDI)— ...

  • Page 8

    ... DMA transfers and gain access to the external bus. CPA is an open drain output that is connected to both ADSP-21065Ls in the system. The CPA pin has an internal 5 kW pull-up resistor. If core access priority is not required in a system, leave the CPA pin unconnected ...

  • Page 9

    ... SDRAM. It drives 2x clock out on the SDCLKx pins for the SDRAM interface to use. See also SDCLKx. Connecting the 1x external clock to CLKIN while leaving XTAL unconnected configures the ADSP-21065L to use the external clock source. The instruction cycle rate is equal to 2x CLKIN. CLKIN may not be halted, changed, or operated below the specified frequency. RESET I/A Processor Reset ...

  • Page 10

    ... O/T SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with a host access. XTAL O Crystal Oscillator Terminal. Used in conjunction with CLKIN to enable the ADSP-21065L’s internal clock generator or to disable it to use an external clock source. See CLKIN. PWM_EVENT I/O/A PWM Output/Event Capture. In PWMOUT mode output pin and functions as a timer 1-0 counter ...

  • Page 11

    ... BTRST to GND and tie or pull-up BTCK asserted after power-up (through BTRST on the connector) or held low for proper operation of the ADSP-2106x. None of the Bxxx pins (Pins 11) are connected on the EZ-ICE probe. The JTAG signals are terminated on the EZ-ICE probe as follows: ...

  • Page 12

    ... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-21065L features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...

  • Page 13

    ... IDLE16 denotes ADSP-21065L state during execution of IDLE16 instruction. TIMING SPECIFICATIONS General Notes Two speed grades of the ADSP-21065L are offered, 60 MHz and 66 MHz instruction rates. The specifications shown are based on a CLKIN frequency of 30 MHz (t = 33.3 ns). The DT derating allows specifications at other CLKIN frequencies (within the min– ...

  • Page 14

    ... Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal (i.e., for a SIMD system). Not required for multiple ADSP-2106xs communicating over the shared bus (through the external port), because the bus arbitration logic synchronizes itself automatically after reset ...

  • Page 15

    ... IRQ 2-0 t IPW Figure 9. Interrupts 1 1 OUT Enable 11-0 OUT Disable 11-0 t DFO t HFO FLAG OUTPUT t HFI t SFI Figure 10. Flags –15– ADSP-21065L Min Max 0.0 6.0 1.0 –5.0 Min Max –2.0 6.0 1.0 –4.0 –4.0 –1.75 t DFO t DFOD Unit ns ns ...

  • Page 16

    ... Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the ADSP-21065L is the bus master when accessing external memory space. These switching characteristics also apply for bus master synchronous read/write timing (see Synchronous Read/Write—Bus Master below). If these timing requirements are met, the synchronous read/write timing can be ignored (and vice versa) ...

  • Page 17

    ... Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the ADSP-21065L is the bus master when accessing external memory space. These switching characteristics also apply for bus master synchronous read/write timing (see Synchronous Read/Write—Bus Master below). If these timing requirements are met, the synchronous read/write timing can be ignored (and vice versa) ...

  • Page 18

    ... When accessing a slave ADSP-21065L, these switching characteristics must meet the slave’s timing requirements for synchronous read/writes (see Synchronous Read/Write—Bus Slave). The slave ADSP-21065L must also meet these (bus master) timing require- ments for data and acknowledge setup and hold times. ...

  • Page 19

    ... CLKIN t DADRO ADDRESS SW ACK (IN) READ CYCLE RD DATA (IN) WRITE CYCLE t WR DATA (OUT) REV DAAK t DRWL DRWL t DDATO Figure 13. Synchronous Read/Write—Bus Master –19– ADSP-21065L t HADRO t HACKC t SACKC t DRDO t HSDATI t SSDATI t DWRO t DATTR ...

  • Page 20

    ... ADSP-21065L Synchronous Read/Write—Bus Slave Use these specifications for ADSP-21065L bus master accesses of a slave’s IOP registers or internal memory (in multiprocessor memory space). The bus master must meet these (bus slave) timing requirements. Parameter Timing Requirements: Address, SW Setup Before CLKIN t SADRI ...

  • Page 21

    ... CLKIN ADDRESS SW ACK READ ACCESS RD DATA (OUT) WRITE ACCESS WR DATA (IN) REV SADRI t DACK t SRWLI t SDDATO t SRWLI Figure 14. Synchronous Read/Write—Bus Slave –21– ADSP-21065L t HADRI t ACKTR t t HRWLI RWHPI t DATTR t t RWHPI HRWLI t HDATWH t SDATWH ...

  • Page 22

    ... NOTES 1 For first asynchronous access after HBR and CS asserted, ADDR low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the Host Processor Control of the ADSP-21065L section of the ADSP-21065L SHARC User’s Manual, Second Edition. 2 Only required for recognition in the current cycle. ...

  • Page 23

    ... HBR CS t DRDYCS REDY (O/D) REDY (A/D) HBG (OUT O/D = OPEN DRAIN, A/D = ACTIVE DRIVE Figure 15. Multiprocessor Bus Request and Host Bus Request REV HHBRI t DHBGO t HHBGO t DBRO t HBRO t DCPAO t SHBGI t SBRI t TRDYHG t HBGRCSV –23– ADSP-21065L t TRCPA t HHBGI t HBRI t ARDYTR ...

  • Page 24

    ... Use these specifications for asynchronous host processor accesses of an ADSP-21065L, after the host has asserted CS and HBR (low). After the ADSP-21065L returns HBG, the host can drive the RD and WR pins to access the ADSP-21065L’s IOP registers. HBR and HBG are assumed low for this timing. Writes can occur at a minimum interval of (1/2) t ...

  • Page 25

    ... READ CYCLE ADDRESS/CS RD DATA (OUT) REDY (O/D) REDY (A/D) WRITE CYCLE ADDRESS CS WR DATA (IN) REDY (O/D) REDY (A/D) O/D = OPEN DRAIN, A/D = ACTIVE DRIVE Figure 16. Asynchronous Read/Write—Host to ADSP-21065L REV SADRDL t SDATRDY t t DRDYRDL RDYPRD t SCSWRL t WWRL t t DRDYWRL RDYPWR –25– ...

  • Page 26

    ... ADSP-21065L Three-State Timing—Bus Master, Bus Slave, HBR, SBTS These specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to CLKIN and the SBTS pin. This timing is applicable to bus master transition cycles (BTC) and host transition cycles (HTC) as well as the SBTS pin. ...

  • Page 27

    ... CLKIN SBTS MIENA, MIENS, MIENHG MEMORY INTERFACE t DATEN DATA t ACKEN ACK HBG MEMORY INTERFACE MEMORY INTERFACE = ADDRESS, RD, WR, MSx, SW, DMAGx. BMS (IN EPROM BOOT MODE) REV STSCK t HTSCK MITRA, MITRS, MITRHG t DATTR t ACKTR t MENHBG Figure 17. Three-State Timing –27– ADSP-21065L t MTRHBG ...

  • Page 28

    ... ADSP-21065L DMA Handshake These specifications describe the three DMA handshake modes. In all three modes DMAR is used to initiate transfers. For hand- shake mode, DMAG controls the latching or enabling of data externally. For external handshake mode, the data transfer is controlled , RD, WR, SW the ADDR 23-0 ...

  • Page 29

    ... CLKIN t SDRLC DMARx DMAGx TRANSFERS BETWEEN ADSP-2106x INTERNAL MEMORY AND EXTERNAL DEVICE DATA (FROM ADSP-2106x TO EXTERNAL DEVICE) DATA (FROM EXTERNAL DEVICE TO ADSP-2106x) TRANSFERS BETWEEN EXTERNAL DEVICE AND EXTERNAL MEMORY (EXTERNAL HANDSHAKE MODE) WR (EXTERNAL DEVICE TO EXTERNAL MEMORY) RD (EXTERNAL MEMORY TO EXTERNAL DEVICE) ADDRESS ...

  • Page 30

    ... ADSP-21065L SDRAM Interface—Bus Master Use these specifications for ADSP-21065L bus master accesses of SDRAM. Parameter Timing Requirements: t Data Setup Before SDCLK SDSDK t Data Hold After SDCLK HDSDK Switching Characteristics: t First SDCLK Rise Delay After CLKIN DSDK1 t Second SDCLK Rise Delay After CLKIN ...

  • Page 31

    ... SDRAM CONTROLLER ADDS ONE SDRAM CLK THREE-STATED CYCLE DELAY ( REV DSDK2 t SDK t HDSDK t t HCADSDK t SSDKC2 t SSDKC1 t SCSDK t HCSDK , RAS, CAS, SDWE, DQM, AND SDA10. Figure 19. SDRAM Interface –31– ADSP-21065L t SDKH t SDKL t SDTRSDK HCADSDK t SDCTR t SDATR t / READ FOLLOWED BY A WRITE. CK ...

  • Page 32

    ... ADSP-21065L Serial Ports Parameter External Clock Timing Requirements: t TFS/RFS Setup Before TCLK/RCLK SFSE t TFS/RFS Hold After TCLK/RCLK HFSE t Receive Data Setup Before RCLK SDRE t Receive Data Hold After RCLK HDRE t TCLK/RCLK Width SCLKW t TCLK/RCLK Period SCLK Internal Clock Timing Requirements: t TFS Setup Before TCLK ...

  • Page 33

    ... TFS DT TCLK / RCLK TCLK / RCLK CLKIN t DPTR SPORT ENABLE AND SPORT DISABLE DELAY THREE-STATE FROM INSTRUCTION LATENCY IS TWO CYCLES t DCLK LOW TO HIGH ONLY Figure 20. Serial Ports –33– ADSP-21065L DRIVE SAMPLE EDGE EDGE t SCLKW t DFSE t HOFSE t t SFSE HFSE t t SDRE ...

  • Page 34

    ... ADSP-21065L EXTERNAL RFS with MCE = 1, MFD = 0 RCLK RFS DT LATE EXTERNAL TFS TCLK TFS DT Figure 21. External Late Frame Sync (Frame Sync Setup < t EXTERNAL RFS with MCE = 1, MFD = 0 RCLK RFS DT LATE EXTERNAL TFS TCLK TFS DT Figure 22. External Late Frame Sync (Frame Sync Setup > t ...

  • Page 35

    ... DMAR 1 0 DMAG2 TCK t t STAP HTAP t DTDO t DSYS Figure 23. JTAG Test Access Port and Emulation –35– ADSP-21065L Max CK 11.0 15 IRQ , ID , FLAG , DR0x, DR1x, TCLK0, 2 2-1 1-0 2-0 11-0 , RAS, CAS, SDWE, SDCKE, PWM_EVENTx. , CPA, FLAG , PWM_EVENTx, DT0x, DT1x, 2-1 ...

  • Page 36

    ... Example System Hold Time Calculation To determine the data output hold time in a particular system, first calculate the difference between the ADSP-21065L’s output voltage OH 3.1V, +85 C and the input threshold for the device requiring the hold time. A typical DV will be 0 ...

  • Page 37

    ... Figure 29. Typical Rise and Fall Time (0.8 V–2 FALL TIME 140 160 180 200 –1 –2 –37– ADSP-21065L RISE TIME FALL TIME 100 120 140 160 LOAD CAPACITANCE – 100 120 140 160 LOAD CAPACITANCE – pF Figure 30 ...

  • Page 38

    ... Note also that it is not common for an appli- cation to have 100% or even 50% of the outputs switching simultaneously. ENVIRONMENTAL CONDITIONS Thermal Characteristics The ADSP-21065L is offered in a 208-lead MQFP and a 196- ball Mini-BGA package. The ADSP-21065L is specified for a case temperature (T ¥ ensure that T used ...

  • Page 39

    ... VDD FLAG9 121 DATA24 FLAG8 122 DATA25 GND 123 DATA26 DATA0 124 VDD DATA1 125 GND DATA2 126 DATA27 –39– ADSP-21065L Pin Pin Pin Pin No. Name No. Name 127 DATA28 169 ADDR17 128 DATA29 170 ADDR16 129 GND 171 ADDR15 ...

  • Page 40

    ... CAS 43 SDWE 44 45 VDD DQM 46 SDCKE 47 SDA10 48 GND 49 DMAG1 50 DMAG2 51 HBG 52 208-LEAD MQFP PIN OO ADSP-21065L TOP VIEW (Not to Scale CONNECT –40– 156 VDD 155 GND 154 GND 153 BMS 152 BSEL 151 TCK 150 GND 149 TMS 148 TDI 147 ...

  • Page 41

    ... NOTES: 1. THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 FROM ITS IDEAL POSITION WHEN MEASURED IN THE LATERAL DIRECTION. 2. CENTER DIMENSIONS ARE NOMINAL. 3. DIMENSIONS ARE IN MILLIMETERS AND COMPLY WITH JEDEC STANDARD MS-029, FA-1. –41– ADSP-21065L 30.85 30.60 SQ 30.35 157 156 28.20 TOP VIEW 28 ...

  • Page 42

    ... ADSP-21065L Ball # Name Ball # A1 NC1 B1 A2 NC2 B2 A3 FLAG2 B3 A4 ADDR0 B4 A5 ADDR3 B5 A6 ADDR6 B6 A7 ADDR7 B7 A8 ADDR8 B8 A9 ADDR11 B9 A10 ADDR14 B10 A11 ADDR17 B11 A12 ADDR18 B12 A13 NC8 B13 A14 NC7 B14 F1 TCLK1 G1 F2 DR1B G2 F3 DR1A ...

  • Page 43

    ... GND GND GND DATA8 VDD VDD VDD VDD DATA5 DATA2 FLAG10 ACK CPA DATA4 DATA1 FLAG11 MS1 GND FLAG8 FLAG9 MS3 MS2 MS0 –43– ADSP-21065L ADDR3 ADDR0 FLAG2 NC2 NC1 B IRQ0 ADDR2 FLAG0 RFS0 DR0A C ADDR1 FLAG3 IRQ2 RCLK0 TCLK0 ...

  • Page 44

    ... CENTER DIMENSIONS ARE NOMINAL. Revision History Location 6/03—Data Sheet changed from REV REV. C. Edit to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Removal of overbar from DQM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal Edit to POWER DISSIPATION ADSP-21065L (equations above Table III Addition to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Update to OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41, 44 ORDERING GUIDE Instruction Rate ...