ADSP-21065LCSZ-240 Analog Devices Inc, ADSP-21065LCSZ-240 Datasheet - Page 26

• Manufacturer Part Number: ADSP-21065LCSZ-240
• Description: ADSP-21065L 60 Mhz
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21065LCSZ-240

• Interface: Host Interface, Serial Port
• Clock Rate: 60MHz
• Non-volatile Memory: External
• On-chip Ram: 64kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Format: Floating Point
• Clock Freq (max): 60MHz
• Mips: 60
• Device Input Clock Speed: 60MHz
• Ram Size: 68KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.13V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: MQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADS-P21065LCSZ240; ADS-P21065LCSZ240

ADSP-21065L
Three-State Timing—Bus Master, Bus Slave, HBR, SBTS
These specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to CLKIN and
the SBTS pin. This timing is applicable to bus master transition cycles (BTC) and host transition cycles (HTC) as well as the SBTS pin.
Parameter
Timing Requirements:
t
t
Switching Characteristics:
t
t
t
t
t
t
t
t
t
t
t
t
NOTES
1
2
3
Strobes = RD, WR, SW, DMAG.
In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.
Memory Interface = Address, RD, WR, MSx, SW, DMAGx, BMS (in EPROM boot mode).
STSCK
HTSCK
MIENA
MIENS
MIENHG
MITRA
MITRS
MITRHG
DATEN
DATTR
ACKEN
ACKTR
MTRHBG
MENHBG
SBTS Setup Before CLKIN
SBTS Hold Before CLKIN
Address/Select Enable After CLKIN
Strobes Enable After CLKIN
HBG Enable After CLKIN
Address/Select Disable After CLKIN
Strobes Disable After CLKIN
HBG Disable After CLKIN
Data Enable After CLKIN
Data Disable After CLKIN
ACK Enable After CLKIN
ACK Disable After CLKIN
Memory Interface Disable Before HBG Low
Memory Interface Enable After HBG High
2
2
2
2
1
1
3
3
–26–
Min
7.0 + 8 DT
1.0 – 2 DT
–0.5 – 2 DT
2.0 – 2 DT
10.0 + 5 DT
1.0 – 2 DT
7.5 + 4 DT
1.0 – 2 DT
2.0 + 2 DT
15.75 + DT
Max
1.0 + 8 DT
3.0 – 4 DT
4.0 – 4 DT
5.5 – 4 DT
7.0 – 2 DT
6.0 – 2 DT
REV. C
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns