ADSP-21065LCSZ-240 Analog Devices Inc, ADSP-21065LCSZ-240 Datasheet - Page 18

• Manufacturer Part Number: ADSP-21065LCSZ-240
• Description: ADSP-21065L 60 Mhz
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21065LCSZ-240

• Interface: Host Interface, Serial Port
• Clock Rate: 60MHz
• Non-volatile Memory: External
• On-chip Ram: 64kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Format: Floating Point
• Clock Freq (max): 60MHz
• Mips: 60
• Device Input Clock Speed: 60MHz
• Ram Size: 68KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.13V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: MQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADS-P21065LCSZ240; ADS-P21065LCSZ240

ADSP-21065L
Synchronous Read/Write—Bus Master
Use these specifications for interfacing to external memory systems that require CLKIN-relative timing or for accessing a slave
ADSP-21065L (in multiprocessor memory space). These synchronous switching characteristics are also valid during asynchronous
memory reads and writes (see Memory Read—Bus Master and Memory Write—Bus Master).
When accessing a slave ADSP-21065L, these switching characteristics must meet the slave’s timing requirements for synchronous
read/writes (see Synchronous Read/Write—Bus Slave). The slave ADSP-21065L must also meet these (bus master) timing require-
ments for data and acknowledge setup and hold times.
Parameter
Timing Requirements:
t
t
t
t
t
Switching Characteristics:
t
t
t
t
t
t
t
t
t
W = (number of wait states specified in WAIT register) ¥ t
NOTES
1
2
3
Data Hold: User must meet t
ACK is not sampled on external memory accesses that use the Internal wait state mode. For the first CLKIN cycle of a new external memory access, ACK must be
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
SSDATI
HSDATI
DAAK
SACKC
HACK
DADRO
HADRO
DRDO
DWRO
DRWL
DDATO
DATTR
DBM
HBM
times given capacitive and dc loads.
valid by t
subsequent cycles of a wait stated external memory access, synchronous specifications t
(Both, after internal wait states have completed).
DAAK
or t
DSAK
Data Setup Before CLKIN
Data Hold After CLKIN
ACK Delay After Address, MSx, SW, BMS
ACK Setup Before CLKIN
ACK Hold After CLKIN
Address, MSx, BMS, SW Delay After CLKIN
Address, MSx, BMS, SW Hold After CLKIN
RD High Delay After CLKIN
WR High Delay After CLKIN
RD/WR Low Delay After CLKIN
Data Delay After CLKIN
Data Disable After CLKIN
BMSTR Delay After CLKIN
BMSTR Hold After CLKIN
or synchronous specification t
HDA
or t
HDRH
or synchronous specification t
3
1
SACKC
CK
for wait state modes External, Either, or Both (Both, if the internal wait state is zero). For the second and
.
HDATI
1, 2
1
. See system hold time calculation under test conditions for the calculation of hold
–18–
SACKC
and t
Min
0.25 + 2 DT
4.0 – 2 DT
2.75 + 4 DT
2.0 – 4 DT
0.5 – 2 DT
0.5 – 2 DT
0.0 – 3 DT
7.5 + 4 DT
1.0 – 2 DT
–4.0
HACKC
must be met for wait state modes External, Either, or Both
Max
24.0 + 30 DT + W
7.0 – 2 DT
6.0 – 2 DT
6.0 – 3 DT
11.75 + 4 DT
22.0 + 10 DT
7.0 – 2 DT
3.0
REV. C
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns