ADSP-21065LCSZ-240 Analog Devices Inc, ADSP-21065LCSZ-240 Datasheet - Page 17

• Manufacturer Part Number: ADSP-21065LCSZ-240
• Description: ADSP-21065L 60 Mhz
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21065LCSZ-240

• Interface: Host Interface, Serial Port
• Clock Rate: 60MHz
• Non-volatile Memory: External
• On-chip Ram: 64kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Format: Floating Point
• Clock Freq (max): 60MHz
• Mips: 60
• Device Input Clock Speed: 60MHz
• Ram Size: 68KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.13V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: MQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADS-P21065LCSZ240; ADS-P21065LCSZ240

Memory Write—Bus Master
Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN.
These specifications apply when the ADSP-21065L is the bus master when accessing external memory space. These switching
characteristics also apply for bus master synchronous read/write timing (see Synchronous Read/Write—Bus Master below). If these
timing requirements are met, the synchronous read/write timing can be ignored (and vice versa). An exception to this is the ACK pin
timing requirements as described in the note below.
Parameter
Timing Requirements:
t
t
Switching Characteristics:
t
t
t
t
t
t
t
t
t
t
W = (number of wait states specified in WAIT register) ¥ t
H = t
I = t
NOTES
1
2
3
REV. C
ACK is not sampled on external memory accesses that use the Internal wait state mode. For the first CLKIN cycle of a new external memory access, ACK must be
The falling edge of MSx, SW, and BMS is referenced.
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
DAAK
DSAK
DAWH
DAWL
WW
DDWH
DWHA
DATRWH
WWR
WRDGL
DDWR
WDE
valid by t
subsequent cycles of a wait stated external memory access, synchronous specifications t
(Both, after internal wait states have completed).
CK
CK
(if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
(if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
DAAK
ADDRESS
or t
MSx , SW
DMAG
DSAK
ACK Delay from Address
ACK Delay from WR Low
Address, Selects to WR Deasserted
Address, Selects to WR Low
WR Pulsewidth
Data Setup Before WR High
Address Hold After WR Deasserted
Data Disable After WR Deasserted
WR High to WR, RD Low
WR High to DMAGx Low
Data Disable Before WR or RD Low
WR Low to Data Enabled
DATA
BMS
ACK
WR
RD
or synchronous specification t
t
DAWL
1, 2
t
DAAK
1
SACKC
2
Figure 12. Memory Write—Bus Master
CK
for wait state modes External, Either, or Both (Both, if the internal wait state is zero). For the second and
.
t
DSAK
3
2
t
WDE
t
DAWH
–17–
t
WW
SACKC
and t
Min
29.0 + 31 DT + W
3.5 + 6 DT
24.5 + 25 DT + W
15.5 + 19 DT + W
0.0 + 1 DT + H
1.0 + 1 DT + H
4.5 + 7 DT + H
11.0 + 13 DT + H
3.5 + 6 DT + I
4.5 + 6 DT
HACKC
t
DDWH
must be met for wait state modes External, Either, or Both
t
DATRWH
t
DWHA
Max
24.0 + 30 DT + W
19.5 + 24 DT + W
4.0 + 1 DT + H
t
t
WRDGL
ADSP-21065L
WWR
t
DDWR
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns