ADSP-21065LCSZ-240 Analog Devices Inc, ADSP-21065LCSZ-240 Datasheet - Page 2

• Manufacturer Part Number: ADSP-21065LCSZ-240
• Description: ADSP-21065L 60 Mhz
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21065LCSZ-240

• Interface: Host Interface, Serial Port
• Clock Rate: 60MHz
• Non-volatile Memory: External
• On-chip Ram: 64kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Format: Floating Point
• Clock Freq (max): 60MHz
• Mips: 60
• Device Input Clock Speed: 60MHz
• Ram Size: 68KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.13V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: MQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADS-P21065LCSZ240; ADS-P21065LCSZ240

ADSP-21065L
544 Kbits Configurable On-Chip SRAM
Dual-Ported for Independent Access by Core Processor
Configurable in Combinations of 16-, 32-, 48-Bit Data and
DMA Controller
Ten DMA Channels—Two Dedicated to the External Port
Background DMA Transfers at up to 66 MHz, in Parallel
Performs Transfers Between:
and DMA
Program Words in Block 0 and Block 1
and Eight Dedicated to the Serial Ports
with Full Speed Processor Execution
Internal RAM and Host
Internal RAM and Serial Ports
Internal RAM and Master or Slave SHARC
Internal RAM and External Memory or I/O Devices
External Memory and External Devices
–2–
Host Processor Interface
Efficient Interface to 8-, 16-, and 32-Bit Microprocessors
Host Can Directly Read/Write ADSP-21065L IOP Registers
Multiprocessing
Distributed On-Chip Bus Arbitration for Glueless, Parallel
132 Mbytes/s Transfer Rate Over Parallel Bus
Serial Ports
Independent Transmit and Receive Functions
Programmable 3-Bit to 32-Bit Serial Word Width
I
Glueless Interface to Industry Standard Codecs
TDM Multichannel Mode with -Law/A-Law Hardware
Multichannel Signaling Protocol
2
S Support Allowing Eight Transmit and Eight Receive
Bus Connect Between Two ADSP-21065Ls Plus Host
Channels
Companding
REV. C