ADSP-BF526KBCZ-4 Analog Devices Inc, ADSP-BF526KBCZ-4 Datasheet
ADSP-BF526KBCZ-4
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ADSP-BF526KBCZ-4 Summary of contents
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... USB EXTERNAL PORT FLASH, SDRAM CONTROL *REGULATOR ONLY AVAILABLE ON ADSP-BF523/ADSP-BF525/ADSP-BF527 PROCESSORS Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use ...
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... Revised footnotes in Voltage ................................................................ 36 /V power is Added characterization data for ADSP-BF522/ADSP-BF524/ DDEXT DDMEM ADSP-BF526 processors (and revised all timing diagrams for clarity/consistency) in Min specifications and Operat- Revised specifications in the following sections: NAND Flash Controller Interface Timing .................... 42 Serial Ports ........................................................... 52 HOSTDP A/C Timing- Host Read Cycle ...................... 63 HOSTDP A/C Timing- Host Write Cycle ...
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... DMA (HOSTDP) interface, and a parallel peripheral interface (PPI PROCESSOR PERIPHERALS The ADSP-BF52x processors contain a rich set of peripherals connected to the core via several high bandwidth buses, provid- ing flexibility in system configuration as well as excellent overall system performance (see the block diagram These Blackfin processors contain dedicated network commu ...
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... ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 regulator provides a range of core voltage levels when supplied from V . The voltage regulator can be bypassed at the user's DDEXT discretion. BLACKFIN PROCESSOR CORE As shown in Figure 2, the Blackfin processor core contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs, four video ALUs, and a 40-bit shifter. The computation units process 8-, 16-, or 32-bit data from the register file ...
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... ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 length, and base registers (for circular buffering), and eight additional 32-bit pointer registers (for C-style indexed stack manipulation). Blackfin processors support a modified Harvard architecture in combination with a hierarchical memory structure. Level 1 (L1) memories are those that typically operate at the full processor speed with little or no latency ...
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... NAND Flash Controller (NFC) The ADSP-BF52x processors provide a NAND flash controller (NFC). NAND flash devices provide high-density, low-cost memory. However, NAND flash devices also have long random access times, invalid blocks, and lower reliability over device lifetimes ...
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... ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 controller to prioritize and control all system events. Conceptu- ally, interrupts from the peripherals enter into the SIC and are then routed directly into the general-purpose interrupts of the CEC. Core Event Controller (CEC) The CEC supports nine general-purpose interrupts (IVG15–7), in addition to the dedicated interrupt and exception events ...
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... ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 3. System Interrupt Controller (SIC) (Continued) Peripheral Interrupt Event OTP Memory Interrupt GP Counter DMA Channel 1 (MAC RX/HOSTDP) Port H Interrupt A DMA Channel 2 (MAC TX/NFC) Port H Interrupt B Timer 0 Timer 1 Timer 2 Timer 3 Timer 4 Timer 5 Timer 6 Timer 7 Port G Interrupt A Port G Interrupt B MDMA Stream 0 MDMA Stream 1 ...
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... ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 unmasked and is processed by the system when asserted. A cleared bit in the register masks the peripheral event, pre- venting the processor from servicing the event. • SIC interrupt status registers (SIC_ISRx) — As multiple peripherals can be mapped to a single event, these registers allow the software to determine which peripheral event source triggered the interrupt ...
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... ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 REAL-TIME CLOCK The real-time clock (RTC) provides a robust set of digital watch features, including current time, stopwatch, and alarm. The RTC is clocked by a 32.768 kHz crystal external to the Blackfin processor. Connect RTC pins RTXI and RTXO with external components as shown in Figure 4 ...
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... ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 SERIAL PORTS The processors incorporate two dual-channel synchronous serial ports (SPORT0 and SPORT1) for serial and multiproces- sor communications. The SPORTs support the following features: 2 • capable operation. • Bidirectional operation — Each SPORT has two sets of independent transmit and receive pins, enabling eight ...
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... CMOS camera sensor devices. 10/100 ETHERNET MAC The ADSP-BF526 and ADSP-BF527 processors offer the capa- bility to directly connect to a network by way of an embedded Fast Ethernet Media Access Controller (MAC) that supports both 10-BaseT (10M bits/sec) and 100-BaseT (100M bits/sec) operation ...
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... PPI_CONTROL register. Frame Capture Mode Frame capture mode allows the video source(s) to act as a slave (for frame capture for example). The ADSP-BF52x processors control when to read from the video source(s). PPI_FS1 is an HSYNC output, and PPI_FS2 is a VSYNC output. Output Mode Output mode is used for transmitting video or other data with up to three output frame syncs ...
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... For more information about PLL controls, see the “Dynamic Power Management” chapter in the ADSP-BF52x Blackfin Pro- cessor Hardware Reference. Sleep Operating Mode—High Dynamic Power Savings The sleep mode reduces dynamic power dissipation by disabling the clock to the processor core (CCLK) ...
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... The Ethernet or USB modules can wake up the internal supply regulator (ADSP-BF525 and ADSP-BF527 only) or signal an external regulator to wake up using EXT_WAKE0 or EXT_WAKE1. If PG15 does not connect as a PHYINT signal to an external PHY device, PG15 can be pulled low by any other device to wake the processor up ...
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... In this way, the startup time of the external regulator is detected after hibernation. For a complete description of Soft Start and Power Good functionality, refer to the ADSP-BF52x Blackfin Processor Hardware Reference. ADSP-BF522/ADSP-BF524/ADSP-BF526 VOLTAGE REGULATION The ADSP-BF522/ADSP-BF524/ADSP-BF526 processor V ...
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... Figure 6. A design procedure for third-overtone oper- ation is discussed in detail in application note (EE-168) Using Third Overtone Crystals with the ADSP-218x DSP on the Analog Devices website (www.analog.com)—use site search on “EE-168.” The CLKBUF pin is an output pin, which is a buffered version of the input clock ...
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... ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 The maximum CCLK frequency not only depends on the part's maximum instruction rate (see Page 87). This frequency also depends on the applied V voltage. See DDINT Table 15 for details. The maximal system clock rate (SCLK) depends on the chip package and the applied V and V ...
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... ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 2 version 2. multiplexer can be used to select one processor at a time when booting multiple processors from a single TWI. • Boot from UART0 host on Port G (BMODE = 0x7) — Using an autobaud handshake sequence, a boot-stream for- matted program is downloaded by the host. The host selects a bit rate within the UART clocking capabilities. ...
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... By programming OTP memory, the user can also instruct the pre-boot routine to customize the PLL, Internal Voltage Regulator (ADSP-BF523/ADSP-BF525/ADSP-BF527 only), SDRAM Controller, and Asynchronous Memory Controller. The boot kernel differentiates between a regular hardware reset and a wakeup-from-hibernate event to speed up booting in the later case ...
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... Blackfin processors also fully emulates the ADSP-BF52x processors. EZ-KIT Lite Evaluation Board For evaluation of ADSP-BF52x processors, use the EZ-KIT Lite boards available from Analog Devices. Order using part num- bers ADZS-BF526-EZLITE or ADZS-BF527-EZLITE. The boards come with on-chip emulation capabilities and are equipped to enable software development ...
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... ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 SIGNAL DESCRIPTIONS Signal definitions for the ADSP-BF52x processors are listed in Table 10. In order to maintain maximum function and reduce package size and ball count, some balls have dual, multiplexed functions. In cases where ball function is reconfigurable, the default state is shown in plain text, while the alternate function is shown in italics ...
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... ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 10. Signal Descriptions (Continued) Signal Name USB 2.0 HS OTG USB_DP USB_DM USB_XI USB_XO USB_ID USB_VREF USB_RSET USB_VBUS Port F: GPIO and Multiplexed Peripherals PF0/PPI D0/DR0PRI /ND_D0A PF1/PPI D1/RFS0/ND_D1A PF2/PPI D2/RSCLK0/ND_D2A PF3/PPI D3/DT0PRI/ND_D3A PF4/PPI D4/TFS0/ND_D4A/TACLK0 PF5/PPI D5/TSCLK0/ND_D5A/TACLK1 PF6/PPI D6/DT0SEC/ND_D6A/TACI0 PF7/PPI D7/DR0SEC/ND_D7A/TACI1 PF8/PPI D8/DR1PRI ...
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... ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 10. Signal Descriptions (Continued) Signal Name Port G: GPIO and Multiplexed Peripherals PG0/HWAIT PG1/SPISS/SPISEL1 PG2/SCK PG3/MISO/DR0SECA PG4/MOSI/DT0SECA PG5/TMR1/PPI_FS2 PG6/DT0PRIA/TMR2/PPI_FS3 PG7/TMR3/DR0PRIA/UART0TX PG8/TMR4/RFS0A/UART0RX/TACI4 PG9/TMR5/RSCLK0A/TACI5 PG10/TMR6/TSCLK0A/TACI6 PG11/TMR7/HOST_WR PG12/DMAR1/UART1TXA/HOST_ACK PG13/DMAR0/UART1RXA/HOST_ADDR/TACI2 PG14/TSCLK0A1/MDC/HOST_RD 3 PG15 /TFS0A/MII PHYINT/RMII MDINT/HOST_CE I/O Port H: GPIO and Multiplexed Peripherals PH0/ND_D0/MIICRS/RMIICRSDV/HOST_D0 PH1/ND_D1/ERxER/HOST_D1 PH2/ND_D2/MDIO/HOST_D2 PH3/ND_D3/ETxEN/HOST_D3 ...
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... RESET NMI BMODE3–0 ADSP-BF523/ADSP-BF525/ADSP-BF527 Voltage Regulation I/F VR SEL VR /EXT_WAKE1 OUT EXT_WAKE0 SS/PG ADSP-BF522/ADSP-BF524/ADSP-BF526 Voltage Regulation I/F EXT_WAKE1 EXT_WAKE0 PG Type Function I/O PPI Frame Sync1/Timer0 I PPI Clock/Timer Clock I/O 5V TWI Serial Clock (This pin is an open-drain output and requires a pull-up 4 resistor. ...
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... C specification for the proper resistor value. Type Function ALL SUPPLIES MUST BE POWERED See Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors on Page 29, and see Operating Conditions for ADSP-BF522/ ADSP-BF524/ADSP-BF526 Processors on Page P I/O Power Supply P Internal Power Supply P Real Time Clock Power Supply P 3.3 V USB Phy Power Supply ...
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... When not using the USB peripheral on the ADSP-BF524/ADSP-BF526 or terminating V 6 Bidirectional balls (PF15–0, PG15–0, PH15–0) and input balls (RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE3–0) of the ADSP-BF52x processors are 3.3 V tolerant (always accept up to 3.6 V maximum V 7 Parameter value applies to all input and bidirectional balls, except USB_DP, USB_DM, USB_VBUS, SDA, and SCL ...
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... CCLK DDINT 1 See the Ordering Guide on Page 87. 2 Applies to 400 MHz models only. See the Ordering Guide on Page Table 13. Phase-Locked Loop Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors Parameter f Voltage Controlled Oscillator (VCO) Frequency VCO 1 See the Ordering Guide on Page 87. Table 14. SCLK Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors ...
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... When not using the USB peripheral on the ADSP-BF525/ADSP-BF527 or terminating V 9 Bidirectional balls (PF15–0, PG15–0, PH15–0) and input balls (RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE3–0) of the ADSP-BF52x processors are 3.3 V tolerant (always accept up to 3.6 V maximum V 10 Parameter value applies to all input and bidirectional balls, except USB_DP, USB_DM, USB_VBUS, SDA, and SCL ...
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... Applies to 600 MHz models only. See the Ordering Guide on Page 3 Applies to 533 MHz and 600 MHz models only. See the 4 Applies only to automotive products. See Automotive Products on Page Table 16. Phase-Locked Loop Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors Parameter f Voltage Controlled Oscillator (VCO) Frequency VCO (Commercial/Industrial Models) f ...
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... ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 ELECTRICAL CHARACTERISTICS Table 18. Common Electrical Characteristics for All ADSP-BF52x Processors Parameter V High Level Output Voltage OH V High Level Output Voltage OH V High Level Output Voltage OH V Low Level Output Voltage OL I High Level Input Current Low Level Input Current IL I High Level Input Current JTAG ...
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... Current V PPOTP PPOTP PPOTP I V Current V PPOTP PPOTP PPOTP Write 1 See the ADSP-BF52x Blackfin Processor Hardware Reference Manual for definition of sleep, deep sleep, and hibernate operating modes. 2 Includes current DDEXT DDUSB DDMEM DDOTP 3 Guaranteed maximum specifications. 4 Unit for (Volts). Unit for f is MHz. Example: 1 MHz would be 0.52 × ...
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... I V Current V PPOTP PPOTP PPOTP I V Current V PPOTP PPOTP PPOTP 1 See the ADSP-BF52x Blackfin Processor Hardware Reference Manual for definition of sleep, deep sleep, and hibernate operating modes. 2 Includes current DDEXT DDUSB DDMEM DDOTP 3 Guaranteed maximum specifications. 4 Unit for (Volts). Unit for f is MHz ...
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... DD-PEAK DDINT I DD-HIGH I DD-TYP 25). I DD-APP I DD-NOP I DD-IDLE 1 See Estimating Power for ASDP-BF534/BF536/BF537 Blackfin Processors (EE-297). The power vector information also applies to the ADSP-BF52x processors. (mA) for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors Voltage (V 1.3 V 1.35 V 1.50 1.64 1.89 1.95 2.15 2.22 2.79 2.92 3.57 3.75 4 ...
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... Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors on Page Rev Page May 2010 1 ) 1.20 V 1.25 V 15.4 18.0 19.8 22.9 27.0 30.9 42.1 47.6 55.7 62.5 74.6 83.2 99 ...
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... Duty cycle refers to the percentage of time the signal exceeds the value for the 100% case. The is equivalent to the measured duration of a single instance of overshoot or undershoot as a percentage of the period of occurrence. When programming OTP memory on the ADSP-BF522/ ADSP-BF524/ADSP-BF526 processors, the VPPOTP ball must be set to the write value specified in the ...
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... ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. PACKAGE INFORMATION The information presented in details about the package branding for the ADSP-BF52x proces- sors. For a complete listing of product availability, see Guide on Page 87. Figure 8. Product Information on Package Table 30 ...
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... ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 TIMING SPECIFICATIONS Specifications are subject to change without notice. Clock and Reset Timing Table 31 and Figure 9 describe clock and reset operations. Per the CCLK and SCLK timing specifications in Table 17, combinations of CLKIN and clock multipliers must not select core/peripheral clocks in excess of the processor's maximum instruction rate ...
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... ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 CLKIN V DD_SUPPLIES In Figure t RST_IN_PWR 10 DD_SUPPLIES DDINT DDEXT DDRTC DDUSB Figure 10. Power-Up Reset Timing Rev Page May 2010 , V , and V . DDMEM DDOTP ...
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... PROGRAMMED READ ACCESS 4 CYCLES SARDY HARDY t SARDY t Figure 11. Asynchronous Memory Read Cycle Timing Rev Page May 2010 ADSP-BF523/ADSP-BF525/ ADSP-BF527 V V DDMEM DDMEM 1.8 V Nominal 2.5/3.3 V Nominal Max Min Max Min 2.1 2.1 0.9 0.8 4.0 4.0 0.2 0.2 6 ...
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... CYCLE 1 CYCLE SARDY t HARDY t t ENDAT HARDY t SARDY Figure 12. Asynchronous Memory Write Cycle Timing Rev Page May 2010 ADSP-BF523/ADSP-BF525/ ADSP-BF527 V V DDMEM DDMEM 1.8 V Nominal 2.5/3.3 V Nominal Max Min Max Min 4.0 4.0 0.2 0.2 6.0 6.0 0.0 0.0 6.0 6.0 ...
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... ARE Low to ARE Low RC Timing Requirements (ADSP-BF522/ADSP-BF524/ADSP-BF526) t Data Setup Time for a Read Transaction DRS t Data Hold Time for a Read Transaction DRH Timing Requirements (ADSP-BF523/ADSP-BF525/ADSP-BF527) t Data Setup Time for a Read Transaction DRS t Data Hold Time for a Read Transaction DRH Write Followed by Read Switching Characteristics ...
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... ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 ND_CE ND_CLE ND_ALE AWE ND_DATA Figure 13. NAND Flash Controller Interface Timing — Command Write Cycle ND_CE ND_CLE ND_ALE AWE ND_DATA Figure 14. NAND Flash Controller Interface Timing — Address Write Cycle t t CWL CH t CLEWL t ALEWL DWH t DWS In Figure 13, ND_DATA is ND_D0–D7. ...
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... ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 ND_CE ND_CLE ND_ALE AWE ND_DATA Figure 15. NAND Flash Controller Interface Timing — Data Write Operation ND_CE ND_CLE ND_ALE ARE ND_DATA Figure 16. NAND Flash Controller Interface Timing — Data Read Operation t CWL t CLEWL t ALEWL WHWL t t DWS DWH In Figure 15, ND_DATA is ND_D0–D7. ...
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... ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 ND_CE ND_CLE AWE ARE ND_DATA Figure 17. NAND Flash Controller Interface Timing — Write Followed by Read Operation t CLWL t t CLEWL CLH WHRL t t DWS DWH In Figure 17, ND_DATA is ND_D0–D7. Rev Page May 2010 DRS DRH ...
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... ENSDAT 1 The t value is the inverse of the f specification discussed in SCLK SCLK 2 Command balls include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE. Table 37. SDRAM Interface Timing for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors Parameter Timing Requirements t Data Setup Before CLKOUT SSDAT t Data Hold After CLKOUT HSDAT Switching Characteristics ...
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... ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 CLKOUT DATA (IN) DATA (OUT) COMMAND, ADDRESS (OUT) t SCLK t t SSDAT HSDAT t t ENSDAT t DCAD NOTE: COMMAND = , , , SDQM, Figure 18. SDRAM Interface Timing Rev Page May 2010 t t SCLKL SCLKH t DCAD DSDAT t HCAD t HCAD , SA10, SCKE. ...
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... DMARx Inactive Pulse Width DMARINACT 1 Because the external DMA control pins are part of the V V are NOT equal may require level shifting logic for correct operation. DDMEM Table 39. External DMA Request Timing for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors Parameter Timing Requirements t DMARx Asserted to CLKOUT High Setup DS t ...
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... HOFSPE t Transmit Data Delay After PPI_CLK DDTPE t Transmit Data Hold After PPI_CLK HDTPE 1 PPI_CLK frequency cannot exceed f /2 SCLK Table 41. Parallel Peripheral Interface Timing for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors Parameter Timing Requirements 1 t PPI_CLK Width PCLKW 1 t PPI_CLK Period PCLK Timing Requirements - GP Input and Frame Capture Modes ...
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... ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 DATA SAMPLED / FRAME SYNC SAMPLED PPI_CLK t SFSPE PPI_FS1/2 PPI_DATA PPI_CLK PPI_FS1/2 PPI_DATA FRAME SYNC DRIVEN PPI_CLK t DFSPE t HOFSPE PPI_FS1/2 t SDRPE PPI_DATA DATA SAMPLED / FRAME SYNC SAMPLED t PCLKW t HFSPE t SDRPE Figure 20. PPI GP Rx Mode with External Frame Sync Timing DATA DRIVEN / ...
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... ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 FRAME SYNC DRIVEN PPI_CLK t DFSPE t HOFSPE PPI_FS1/2 PPI_DATA t DDTPE Figure 23. PPI GP Tx Mode with Internal Frame Sync Timing Rev Page May 2010 DATA DATA DRIVEN DRIVEN t PCLK t PCLKW t HDTPE ...
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... SCLKE SCLKE 4.0 × t 4.0 × t SCLKE SCLKE 10.0 3 0.0 0 10.0 3 0.0 0.0 Rev Page May 2010 ADSP-BF523/ADSP-BF525/ ADSP-BF527 V V DDEXT 2.5/3.3V Nominal 1.8V Nominal Max Min Max Min 3.0 3.0 3.0 3.0 3.0 3.0 3.5 3.0 7.0 4.5 2.0 × ...
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... Transmit Data Delay After TSCLKx DDTI t Transmit Data Hold After TSCLKx HDTI 1 Referenced to sample edge. 2 Referenced to drive edge. Table 44. Serial Ports—Internal Clock for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors Parameter Timing Requirements t TFSx/RFSx Setup Before TSCLKx/RSCLKx SFSI t TFSx/RFSx Hold After TSCLKx/RSCLKx HFSI t Receive Data Setup Before RSCLKx ...
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... ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 DATA RECEIVE—INTERNAL CLOCK DRIVE EDGE t SCLKIW RSCLKx t DFSI t HOFSI RFSx (OUTPUT) t SFSI RFSx (INPUT) t SDRI DRx DATA TRANSMIT—INTERNAL CLOCK DRIVE EDGE t SCLKIW TSCLKx t D FSI t HOFSI TFSx (OUTPUT) t SFSI TFSx (INPUT) t DDTI t HDTI DTx TSCLKx (INPUT) TFSx (INPUT) ...
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... SCLK SCLK –2.0 –2 SCLK SCLK DRIVE EDGE DRIVE EDGE t DTENE/I Figure 26. Serial Ports — Enable and Three-State Rev Page May 2010 ADSP-BF523/ADSP-BF525/ ADSP-BF527 V V DDEXT DDEXT 2.5/3.3V Nominal 1.8V Nominal Min Max Min Max 0.0 0 SCLK SCLK –2.0 –2 ...
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... DTENLFSE 1ST BIT DRIVE SAMPLE DRIVE EDGE EDGE EDGE t DDTLFSE 1ST BIT Figure 27. Serial Ports — External Late Frame Sync Rev Page May 2010 ADSP-BF523/ADSP-BF525/ ADSP-BF527 V V DDEXT DDEXT DDEXT 2.5/3.3V Nominal 1.8V Nominal Max Min Max Min 10.0 12.0 0.0 ...
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... SCLK SCLK 6 –1.0 –1 SPICLM SPICHM t HDSPIDM t HDSPIDM t HSPIDM Figure 28. Serial Peripheral Interface (SPI) Port—Master Timing Rev Page May 2010 ADSP-BF523/ADSP-BF525/ ADSP-BF527 V V DDEXT DDEXT 2.5/3.3V Nominal 1.8V Nominal Max Min Max Min 11.6 9.6 –1.5 –1.5 2 × t –1.5 2 × t – ...
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... SPICHS t DDSPID t HDSPID t HSPID t t HDSPID DDSPID t SSPID Figure 29. Serial Peripheral Interface (SPI) Port—Slave Timing Rev Page May 2010 ADSP-BF523/ADSP-BF525/ ADSP-BF527 V V DDEXT DDEXT 2.5/3.3V Nominal 1.8V Nominal Max Min Max Min –1.5 2 × t –1.5 2 × t SCLK SCLK SCLK –1.5 2 × ...
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... USB ADSP-BF522/ADSP-BF524/ ADSP-BF526 V V DDEXT DDEXT 2.5/3.3V Nominal 1.8V Nominal Min Max Min Max 12 33.3 12 33.3 50 –50 50 Rev Page May 2010 ADSP-BF523/ADSP-BF525/ ADSP-BF527 V V DDEXT DDEXT 2.5/3.3V Nominal 1.8V Nominal Min Max Min Max 9 33.3 9 33.3 –50 50 –50 50 Unit MHz ppm ...
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... General-Purpose Port Ball Input Pulse Width WFI Switching Characteristics t General-Purpose Port Ball Output Delay from CLKOUT GPOD Low Table 51. General-Purpose Port Timing for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors Parameter Timing Requirement t General-Purpose Port Ball Input Pulse Width WFI Switching Characteristics t General-Purpose Port Ball Output Delay from CLKOUT Low 0 ...
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... SCLK SCLK TOD t t TIS TIH Figure 31. Timer Cycle Timing Rev Page May 2010 ADSP-BF523/ADSP-BF525/ADSP-BF527 V V DDEXT DDEXT 2.5/3.3V Nominal 1.8V Nominal Min Max Min t t SCLK SCLK t t SCLK SCLK 8.1 6.2 –2 – – ...
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... ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Timer Clock Timing Table 53 and Figure 32 describe timer clock timing. Table 53. Timer Clock Timing Parameter Switching Characteristic t Timer Output Update Delay After PPI_CLK High TODP PPI_CLK TMRx OUTPUT Up/Down Counter/Rotary Encoder Timing Table 54. Up/Down Counter/Rotary Encoder Timing Parameter Timing Requirements ...
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... SCLK 1.0 1 not measured because the number of SCLK cycles for which HOST_ACK is low depends on the Host DMA SCLK Rev Page May 2010 ADSP-BF523/ADSP-BF525/ ADSP-BF527 V V DDEXT DDEXT 2.5/3.3V Nominal 1.8V Nominal Min Max Min Max ...
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... ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 HOST_ADDR HOST_DATA HOST_ACK t t SADRDL t RDWL t t SDATRDY DDARWH t t ACC HDARWH t DRDHRDY t DRDYRDL t RDYPRD In Figure 34, HOST_DATA is HOST_D0–D15. Figure 34. HOSTDP A/C- Host Read Cycle Rev Page May 2010 HADRDH t RDWH ...
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... not measured because the number of SCLK cycles for which HOST_ACK is low depends on the Host DMA FIFO SCLK Rev Page May 2010 ADSP-BF523/ADSP-BF525/ ADSP-BF527 V V DDEXT DDEXT 2.5/3.3V Nominal 1.8V Nominal Min Max Min Max 4 4 2.5 2 ...
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... ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 HOST_ADDR HOST_DATA HOST_ACK t t SADWRL HADWRH t t WRWL t t SDATWH HDATWH t RDYPWR t t DRDYWRL DWRHRDY In Figure 35, HOST_DATA is HOST_D0–D15. Figure 35. HOSTDP A/C- Host Write Cycle Rev Page May 2010 WRWH ...
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... ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 10/100 Ethernet MAC Controller Timing Table 57 through Table 62 and Figure 36 describe the 10/100 Ethernet MAC Controller operations. Table 57. 10/100 Ethernet MAC Controller Timing: MII Receive Signal 1 Parameter Timing Requirements t ERxCLK Frequency (f ERXCLKF t ERxCLK Width (t ERXCLKW ERxCLK t Rx Input Valid to ERxCLK Rising Edge (Data In Setup) ...
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... Rev Page May 2010 V V DDEXT DDEXT 2.5/3.3V Nominal 1.8V Nominal Max Min Max None × 40% t × 60% t × 35% t EREFCLK EREFCLK EREFCLK 4 2 ADSP-BF523/ADSP-BF525/ ADSP-BF527 DDEXT DDEXT DDEXT 2.5/3.3V Nominal 1.8V Nominal Max Min Max Min 8.1 7 Unit MHz × 65 ...
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... ERxCLK × 1.5 t × 1.5 ETxCLK × 1.5 t × 1.5 ERxCLK × 1.5 t × 1.5 ETxCLK × 1.5 t × 1.5 ETxCLK ECRSL ECOLL ADSP-BF523/ADSP-BF525/ ADSP-BF527 V V DDEXT DDEXT DDEXT 2.5/3.3V Nominal 1.8V Nominal Max Min Max Min –1 –1 Unit ...
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... ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 MDC (OUTPUT) MDIO (OUTPUT) MDIO (INPUT) Figure 41. 10/100 Ethernet MAC Controller Timing: MII Station Management t MDCOH t MDCOV t MDIOS Rev Page May 2010 t MDCIH ...
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... ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 JTAG Test And Emulation Port Timing Table 63 and Figure 42 describe JTAG port operations. Table 63. JTAG Port Timing Parameter Timing Requirements t TCK Period TCK t TDI, TMS Setup Before TCK High STAP t TDI, TMS Hold After TCK High HTAP t System Inputs Setup Before TCK High ...
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... ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 OUTPUT DRIVE CURRENTS Figure 43 through Figure 57 show typical current-voltage char- acteristics for the output drivers of the ADSP-BF52x processors. 200 160 120 –40 –80 –120 –160 –200 0 0.5 1.0 1.5 2.0 SOURCE VOLTAGE (V) Figure 43. Driver Type A Current (3.3V V 160 120 – ...
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... ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 100 –20 –40 –60 –80 –100 0 0.5 1.0 1.5 2.0 SOURCE VOLTAGE (V) Figure 49. Driver Type C Current (3. –20 –40 –60 –80 0 0.5 1.0 1.5 SOURCE VOLTAGE (V) Figure 50. Drive Type C Current (2. –10 –20 –30 –40 0 0.5 1.0 SOURCE VOLTAGE (V) Figure 51. Driver Type C Current (1.8V V ...
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... ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 –10 –20 –30 –40 –50 –60 0 0.5 1.0 1.5 2.0 SOURCE VOLTAGE (V) Figure 55. Driver Type E Current (3. –10 –20 –30 –40 0 0.5 1.0 1.5 2.0 SOURCE VOLTAGE (V) Figure 56. Driver Type E Current (2. –5 –10 –15 –20 0 0.5 1.0 1.5 2.0 SOURCE VOLTAGE (V) Figure 57 ...
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... ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Output Disable Time Measurement Output balls are considered to be disabled when they stop driv- ing, go into a high impedance state, and start to decay from their output high or low voltage. The output disable time t difference between t and t DIS_MEASURED DECAY side of Figure 59. ...
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... ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 100 LOAD CAPACITANCE (pF) Figure 62. Driver Type A Typical Rise and Fall Times (10%–90%) vs. Load Capacitance (2.5V V DDEXT 100 LOAD CAPACITANCE (pF) Figure 63. Driver Type A Typical Rise and Fall Times (10%–90%) vs. Load Capacitance (3.3V V DDEXT 100 LOAD CAPACITANCE (pF) Figure 64. Driver Type B Typical Rise and Fall Times (10%–90%) vs. ...
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... ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 RISE 100 LOAD CAPACITANCE (pF) Figure 68. Driver Type C Typical Rise and Fall Times (10%–90%) vs. Load Capacitance (2. DDEXT 100 LOAD CAPACITANCE (pF) Figure 69. Driver Type C Typical Rise and Fall Times (10%–90%) vs. Load Capacitance (3. DDEXT 100 LOAD CAPACITANCE (pF) Figure 70. Driver Type D Typical Rise and Fall Times (10%–90%) vs. ...
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... ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 RISE 100 LOAD CAPACITANCE (pF) Figure 74. Driver Type G Typical Rise and Fall Times (10%–90%) vs. Load Capacitance (2.5V V DDEXT 100 LOAD CAPACITANCE (pF) Figure 75. Driver Type G Typical Rise and Fall Times (10%–90%) vs. Load Capacitance (3.3V V DDEXT ENVIRONMENTAL CONDITIONS To determine the junction temperature on the application ...
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... U2 GND L14 NC DATA4 V1 GND L15 NC DATA5 U1 GND M9 NOTE: In this table, BOLD TYPE indicates the sole signal/function for that ball on ADSP-BF522/ADSP-BF524/ADSP-BF526 processors. 1 For ADSP-BF52xC compatibility, connect this ball to V Table 67 on Page 80 Signal Ball Signal Ball Signal No. No. GND M10 NC D23 PH0 ...
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... DDINT B17 PF11 H9 V DDINT B18 PF12 H10 V DDINT B19 PF13 H11 V DDINT NOTE: In this table, BOLD TYPE indicates the sole signal/function for that ball on ADSP-BF522/ADSP-BF524/ADSP-BF526 processors. 1 For ADSP-BF52xC compatibility, connect this ball to V Ball Signal Ball Signal Ball Signal No. No. ...
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... ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Figure 76 shows the top view of the BC-289-2 CSP_BGA ball configuration. Figure 77 shows the bottom view of the BC-289-2 CSP_BGA ball configuration. KEY: V GND DDINT V I/O DDEXT BALL PAD CORNER TOP VIEW NC V DDMEM Figure 76. 289-Ball CSP_BGA Ball Configuration (Top View Figure 77. 289-Ball CSP_BGA Ball Configuration (Bottom View) Rev ...
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... Y9 GND J12 BMODE3 W9 GND J13 CLKBUF C19 GND K9 CLKIN A11 GND K10 NOTE: In this table, BOLD TYPE indicates the sole signal/function for that ball on ADSP-BF522/ADSP-BF524/ADSP-BF526 processors. Table 69 on Page 83 Signal Ball Signal Ball Signal No. No. GND K11 PF13 A5 PPI_CLK/TMRCLK GND K12 ...
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... PH7 G14 V DDINT B12 PH9 G19 SS/PG B13 PH11 G20 V DDUSB B14 PH12 H1 PG13 B15 PH13 H2 PG14 NOTE: In this table, BOLD TYPE indicates the sole signal/function for that ball on ADSP-BF522/ADSP-BF524/ADSP-BF526 processors. Ball Signal Ball Signal No. No PG8 DDEXT DDEXT H9 GND L8 V H10 ...
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... ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Figure 78 shows the top view of the CSP_BGA ball configura- tion. Figure 79 shows the bottom view of the CSP_BGA ball configuration. A1 BALL PAD CORNER KEY: VDDINT VDDEXT VDDMEM TOP VIEW GND I Figure 78. 208-Ball CSP_BGA Ball Configuration (Top View Figure 79. 208-Ball CSP_BGA Ball Configuration (Bottom View) Rev ...
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... ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 OUTLINE DIMENSIONS Dimensions in the outline dimension figures Figure 81) are shown in millimeters. 12.00 BSC SQ A1 BALL PAD CORNER TOP VIEW 1.40 1.26 1.11 SIDE VIEW NOTES 1. DIMENSIONS ARE IN MILLIMETERS. 2. COMPLIES WITH JEDEC REGISTERED OUTLINE MO-195, VARIATION AJ AND EXCEPTION TO PACKAGE HEIGHT AND BALL HEIGHT. ...
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... NOM 0.30 MIN * 0.50 COPLANARITY 0.12 0.45 0.40 BALL DIAMETER Package Ball Pad Size 0.35 mm diameter 0.50 mm diameter Table 71 are available for use in automotive applica- Package Option BC-208-2 BC-208-2 Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Instruction Rate (Max) 400 MHz 533 MHz ...
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... ADSP-BF525KBCZ-6A 0ºC to +70ºC ADSP-BF526BBCZ-3A –40ºC to +85ºC ADSP-BF526BBCZ-4A –40ºC to +85ºC ADSP-BF526KBCZ-3 0ºC to +70ºC ADSP-BF526KBCZ-4 0ºC to +70ºC ADSP-BF527BBCZ-5A –40ºC to +85ºC ADSP-BF527KBCZ-5 0ºC to +70ºC ADSP-BF527KBCZ-6 0ºC to +70ºC ADSP-BF527KBCZ-6A 0ºC to +70º RoHS Compliant Part ...
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... ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06675-0-5/10(B) Rev Page May 2010 ...