ADSP-BF526KBCZ-4 Analog Devices Inc, ADSP-BF526KBCZ-4 Datasheet - Page 65

• Manufacturer Part Number: ADSP-BF526KBCZ-4
• Description: ADSP-BF526 Processor,400Mhz,Ethernet,USB
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF526KBCZ-4

• Interface: DMA, Ethernet, I²C, PPI, SPI, SPORT, UART, USB
• Clock Rate: 400MHz
• Non-volatile Memory: ROM (32 kB)
• On-chip Ram: 132kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.30V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 289-CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

HOSTDP A/C Timing- Host Write Cycle
Table 56
requirements.
Table 56. Host Write Cycle Timing Requirements
1
Parameter
Timing Requirements
t
t
t
t
t
t
t
Switching Characteristics
t
t
NM (Not Measured) — This parameter is based on t
SADWRL
HADWRH
WRWL
WRWH
DWRHRDY
HDATWH
SDATWH
DRDYWRL
RDYPWR
status and is system design dependent.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
describes the HOSTDP A/C Host Write Cycle timing
HOST_ADDR/HOST_CE Setup
before HOST_WR falling edge
HOST_ADDR/HOST_CE Hold
after HOST_WR rising edge
HOST_WR pulse width low
(ACK mode)
HOST_WR pulse width low
(INT mode)
HOST_WR pulse width high
or time between HOST_WR
rising edge and HOST_RD
falling edge
HOST_WR rising edge delay
after HOST_ACK rising edge
(ACK mode)
Data Hold after HOST_WR rising edge 2.5
Data Setup before HOST_WR
rising edge
HOST_ACK falling edge after HOST_CE
asserted (ACK mode)
HOST_ACK low pulse-width for Write
access (ACK mode)
SCLK
. It is not measured because the number of SCLK cycles for which HOST_ACK is low depends on the Host DMA FIFO
Min
4
2.5
t
t
t
1.5 × t
+ 8.7
2 × t
2.0
3.5
DRDYWRL
RDYPRD
DWRHRDY
1.8V Nominal
Rev. B | Page 65 of 88 | May 2010
SCLK
SCLK
+
ADSP-BF522/ADSP-BF524/
V
+
DDEXT
Max
12.5
NM
ADSP-BF526
1
Min
4
2.5
t
t
t
1.5 × t
+ 8.7
2 × t
2.0
2.5
2.5
2.5/3.3V Nominal
DRDYWRL
RDYPRD
DWRHRDY
SCLK
SCLK
+
V
+
DDEXT
Max
11.5
NM
1
Min
4
2.5
t
t
t
1.5 × t
+ 8.7
2 × t
0
2.5
2.5
DRDYWRL
RDYPRD
DWRHRDY
1.8V Nominal
SCLK
SCLK
+
ADSP-BF523/ADSP-BF525/
V
+
DDEXT
Max
11.5
NM
ADSP-BF527
1
Min
4
2.5
t
t
t
1.5 × t
+ 8.7
2 × t
0
2.5
2.5
2.5/3.3V Nominal
DRDYWRL
RDYPRD
DWRHRDY
SCLK
SCLK
+
V
+
DDEXT
Max
11.5
NM
1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns