ADSP-BF526KBCZ-4 Analog Devices Inc, ADSP-BF526KBCZ-4 Datasheet - Page 28

• Manufacturer Part Number: ADSP-BF526KBCZ-4
• Description: ADSP-BF526 Processor,400Mhz,Ethernet,USB
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF526KBCZ-4

• Interface: DMA, Ethernet, I²C, PPI, SPI, SPORT, UART, USB
• Clock Rate: 400MHz
• Non-volatile Memory: ROM (32 kB)
• On-chip Ram: 132kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.30V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 289-CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 11
register. Set this register prior to using the TWI port.
Table 11. TWI_DT Field Selections and V
1
Clock Related Operating Conditions
for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors
Table 12
ADSP-BF522/ADSP-BF524/ADSP-BF526 processors. Take care
in selecting MSEL, SSEL, and CSEL ratios so as not to exceed the
maximum core clock and system clock (see
describes phase-locked loop operating conditions.
Table 12. Core Clock (CCLK) Requirements (All Instruction Rates
1
2
Table 13. Phase-Locked Loop Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors
1
Table 14. SCLK Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors
1
2
TWI_DT
000 (default)
001
010
011
100
101
110
111 (reserved)
Parameter
f
f
Parameter
f
Parameter
f
f
Designs must comply with the V
See the
Applies to 400 MHz models only. See the
See the
If either V
f
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
CCLK
CCLK
VCO
SCLK
SCLK
SCLK
must be less than or equal to f
Ordering Guide on Page
Ordering Guide on Page
shows settings for TWI_DT in the NONGPIO_DRIVE
describes the core clock timing requirements for the
DDEXT
1
or V
Core Clock Frequency (V
Core Clock Frequency (V
DDMEM
Voltage Controlled Oscillator (VCO) Frequency
CLKOUT/SCLK Frequency (V
CLKOUT/SCLK Frequency (V
are operating at 1.8V nominal, f
V
3.3
1.8
2.5
1.8
3.3
1.8
2.5
–
DDEXT
87.
87.
DDEXT
CCLK
and V
and is subject to additional restrictions for SDRAM interface operation. See
Nominal
Ordering Guide on Page
BUSTWI
DDINT
DDINT
voltages specified for the default TWI_DT setting for correct JTAG boundary scan operation during reset.
=1.33 V minimum)
= 1.235 V minimum)
Table
DDEXT
DDINT
DDINT
SCLK
/V
14).
is constrained to 80 MHz.
≥ 1.33 V)
BUSTWI
< 1.33 V)
Rev. B | Page 28 of 88 | May 2010
V
2.97
1.7
2.97
2.97
4.5
2.25
2.25
–
87.
BUSTWI
Table 13
Min
2
1
) for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors
Nominal Voltage Setting
1.30 V
1.40 V
Min
70
Max
80
80
V
3.3
1.8
3.3
3.3
5
2.5
2.5
–
BUSTWI
1.8 V Nominal
V
DDEXT
Nominal
/V
DDMEM
Table 36 on Page
1
Max
Instruction Rate
Max
100
80
Max
400
300
V
3.63
1.98
3.63
3.63
5.5
2.75
2.75
–
2.5 V/3.3 V Nominal
BUSTWI
2
46.
V
DDEXT
Max
/V
DDMEM
1
Unit
V
V
V
V
V
V
V
–
Unit
MHz
Unit
MHz
MHz
Unit
MHz
MHz