ADSP-BF526KBCZ-4 Analog Devices Inc, ADSP-BF526KBCZ-4 Datasheet - Page 63

• Manufacturer Part Number: ADSP-BF526KBCZ-4
• Description: ADSP-BF526 Processor,400Mhz,Ethernet,USB
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF526KBCZ-4

• Interface: DMA, Ethernet, I²C, PPI, SPI, SPORT, UART, USB
• Clock Rate: 400MHz
• Non-volatile Memory: ROM (32 kB)
• On-chip Ram: 132kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.30V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 289-CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

HOSTDP A/C Timing- Host Read Cycle
Table 55
requirements.
Table 55. Host Read Cycle Timing Requirements
1
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
t
t
NM (Not Measured) — This parameter is based on t
SADRDL
HADRDH
RDWL
RDWL
RDWH
DRDHRDY
SDATRDY
DRDYRDL
RDYPRD
DDARWH
ACC
HDARWH
FIFO status and is system design dependent.
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
describe the HOSTDP A/C Host Read Cycle timing
HOST_ADDR and HOST_CE Setup
before HOST_RD falling edge
HOST_ADDR and HOST_CE Hold
after HOST_RD rising edge
HOST_RD pulse width low
(ACK mode)
HOST_RD pulse width low
(INT mode)
HOST_RD pulse width high or time
between HOST_RD rising edge and
HOST_WR falling edge
HOST_RD rising edge delay after
HOST_ACK rising edge (ACK mode)
Data valid prior HOST_ACK rising
edge (ACK mode)
Host_ACK falling edge after
HOST_CE (ACK mode)
HOST_ACK low pulse-width for
Read access (ACK mode)
Data disable after HOST_RD
Data valid after HOST_RD falling
edge (INT mode)
Data hold after HOST_RD rising
edge
SCLK
. It is not measured because the number of SCLK cycles for which HOST_ACK is low depends on the Host DMA
Min
4
2.5
t
t
t
1.5 × t
+ 8.7
2 × t
2.0
4.5
1.0
DRDYRDL
RDYPRD
DRDHRDY
1.8V Nominal
SCLK
SCLK
+
Rev. B | Page 63 of 88 | May 2010
ADSP-BF522/ADSP-BF524/
V
+
DDEXT
Max
12.5
NM
11.0
1.5 × t
1
ADSP-BF526
SCLK
Min
4
2.5
t
t
t
1.5 × t
+ 8.7
2 × t
2.0
3.5
1.0
2.5/3.3V Nominal
DRDYRDL
RDYPRD
DRDHRDY
SCLK
SCLK
+
V
+
DDEXT
Max
11.25
NM
9.0
1.5 × t
1
SCLK
Min
4
2.5
t
t
t
1.5 × t
+ 8.7
2 × t
0
4.5
1.0
DRDYRDL
RDYPRD
DRDHRDY
1.8V Nominal
SCLK
SCLK
+
ADSP-BF523/ADSP-BF525/
V
+
DDEXT
Max
11.25
NM
9.0
1.5 × t
ADSP-BF527
1
SCLK
Min
4
2.5
t
t
t
1.5 × t
+ 8.7
2 × t
0
3.5
1.0
DRDYRDL
RDYPRD
DRDHRDY
2.5/3.3V Nominal
SCLK
SCLK
+
V
+
DDEXT
Max
11.25
NM
9.0
1.5 × t
1
SCLK
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns