CRD42L51 Cirrus Logic Inc, CRD42L51 Datasheet - Page 27

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CRD42L51

Manufacturer Part Number
CRD42L51
Description
Ref Bd Low-voltage Stereo Codec
Manufacturer
Cirrus Logic Inc
Datasheets
DS679F1
4.2
Power Control
Auto-Detect
Speed Mode
MCLK Divide
Serial Port Master / Slave Selection
Interface Control
ADC Volume & Gain
ADCx High-Pass Filter
ADCx High-Pass Filter Freeze
Line/MIC Input Select
DAC Volume & Gain
DAC De-Emphasis
Signal Processing Engine (SPE)
Data Selection
Channel Mix
Charge Pump Frequency
Hardware Mode
A limited feature-set is available when the CODEC powers up in Hardware Mode (see
er-Up Sequence” on page
functions/features, the default configuration and the associated stand-alone control available.
Feature/Function
Peak Detect and Limiter
MICx Pre-amplifier
Serial Port Master
Serial Port Slave
AOUTx Volume
Tone Control
Digital Boost
Hardware Mode Feature/Function Summary
Noise Gate
Zero Cross
Zero Cross
Soft Ramp
Soft Ramp
Attenuator
41) and may be controlled via stand-alone control pins.
MIC Bias
HP Gain
Table 2. Hardware Mode Feature Summary
CODEC
PGAx
ADCx
DACx
PGAx
Invert
Invert
Beep
ADC
DAC
ADC
DAC
ALC
Mix
Continuous DC Subtraction
Default Configuration
Auto-Detect Speed Mode
Data Input (PCM) to DAC
PCMA = L; PCMB = R
ADCA = L; ADCB = R
Single-Speed Mode
AIN1A to PGAA
AIN1B to PGAB
Powered Down
Powered Down
Powered Up
Powered Up
Powered Up
Powered Up
(Selectable)
(Selectable)
(Selectable)
(Selectable)
G = 0.6047
(64xFs)/7
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
0 dB
0 dB
0 dB
Stand-Alone Control
“MCLKDIV2” pin 2
“I²S/LJ” pin 3
“M/S” pin 29
“DEM” pin 4
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Table 2
“Recommended Pow-
shows a list of
CS42L51
4.5 on page 38
4.5 on page 38
4.6 on page 40
see Section
see Section
see Section
see Section
on page 34
Note
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