CRD42L51 Cirrus Logic Inc, CRD42L51 Datasheet - Page 60

• Manufacturer Part Number: CRD42L51
• Description: Ref Bd Low-voltage Stereo Codec
• Manufacturer: Cirrus Logic Inc

60
6.11
ADCx_ATT7
7
ALCX Zero Cross Disable (ALCX_ZCDIS)
Default: 0
0 - Off
1 - On
Function:
Overrides the ZCROSSx bit setting for the ADC. When this bit is set, the ALC attack rate in the PGA will not
be dictated by the zero cross setting. ALC volume-level changes will take effect immediately in one step.
PGA X Gain Control (PGAX_VOL[4:0])
Default: 00000
Function:
The PGAx Gain Control register allows independent setting of the signal levels in 0.5 dB increments as dic-
tated by the ADCx Soft and Zero Cross bits (SOFTx & ZCROSSx) from +12 dB to -3 dB. Gain settings are
decoded as shown in the table above. The gain changes are implemented as dictated by the ALCX Soft &
Zero Cross bits (ALCX_SZC). Levels are decoded as described in the table above.
Note:
ADCx Attenuator: ADCA (Address 0Ch) & ADCB (Address 0Dh)
ADCX Attenuation Control (ADCX_ATT[7:0])
Default: 00h
Binary Code
Binary Code
0000 0000
1010 0000
1000 0000
0111 1111
1111 1110
1111 1111
ADCx_ATT6
11000
01010
00000
11001
11010
When the ALC is enabled, the PGA is automatically controlled and should not be adjusted manu-
ally.
11110
11111
···
···
···
···
···
···
6
ADCx_ATT5
Volume Setting
Volume Setting
5
+12 dB
-0.5 dB
-96 dB
-96 dB
+5 dB
-1 dB
-3 dB
-3 dB
-1 dB
-2 dB
0 dB
0 dB
0 dB
···
···
···
···
···
···
ADCx_ATT4
4
ADCx_ATT3
3
ADCx_ATT2
2
ADCx_ATT1
1
CS42L51
ADCx_ATT0
DS679F1
0