CS4202-JQZR Cirrus Logic Inc, CS4202-JQZR Datasheet - Page 18

• Manufacturer Part Number: CS4202-JQZR
• Description: IC AC97 W/Headphone Amplifier
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codec '97r

Specifications of CS4202-JQZR

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 90 / 90
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.2
In the serial data input frame, data is passed on the SDATA_IN pin from the CS4202 to the AC ’97 con-
troller. The data format for the input frame is very similar to the output frame. Figure 9 on page 15 illus-
trates the serial port timing.
The PCM capture data from the CS4202 is shifted out MSB first in the most significant 18 bits of each slot.
The least significant 2 bits in each slot will be ‘cleared’. If the host requests PCM data from the AC ’97
Controller that is less than 18 bits wide, the controller should dither and round or just round (but not trun-
cate) to the desired bit depth.
Bits that are reserved or not implemented in the CS4202 will always be returned ‘cleared’.
3.2.1 Serial Data Input Slot Tag Bits (Slot 0)
Codec Ready
Slot 1 Valid
Slot 2 Valid
Slot [3:4,6:8,11] Valid The Slot [3:4,6:8,11] Valid bits indicate Slot [3:4,6:8,11] contains valid capture data from the
Slot 12 Valid
3.2.2 Status Address Port (Slot 1)
RI[6:0]
SR[3:4,6:11]
18
Bit 19 18
Codec
Ready
Bit 15
Res
RI6
AC-Link Serial Data Input Frame
Slot 1
Valid
14
RI5
17
Slot 2
Valid
13
RI4
16
Slot 3
CS4202 ADCs. If a bit is ‘set’, the corresponding input slot contains valid data. If a bit is
‘cleared’, the corresponding slot will be ignored.
Codec Ready. The Codec Ready bit indicates the readiness of the CS4202 AC-link. Immedi-
ately after a Cold Reset this bit will be ‘clear’. Once the CS4202 clocks and voltages are sta-
ble, this bit will be ‘set’. Until the Codec Ready bit is ‘set’, no AC-link transactions should be
attempted by the controller. The Codec Ready bit does not indicate readiness of the DACs,
ADCs, Vref, or any other analog function. Those must be checked in the Powerdown Con-
trol/Status Register (Index 26h) by the controller before any access is made to the mixer reg-
isters. Any accesses to the CS4202 while Codec Ready is ‘clear’ are ignored.
The Slot 1 Valid bit indicates Slot 1 contains a valid read back address.
The Slot 2 Valid bit indicates Slot 2 contains valid register read data.
The Slot 12 Valid bit indicates Slot 12 contains valid GPIO status data.
Register Index. The RI[6:0] bits echo the AC ’97 register address when a register read has
been requested in the previous frame. The CS4202 will only echo the register index for a read
access. Write accesses will not return valid data in Slot 1.
Slot Request. If SRx is ‘set’, this indicates the CS4202 SRC does not need a new sample on
the next AC-link frame for that particular slot. If SRx is ‘clear’, the SRC indicates a new sample
is needed on the following frame. If the VRA bit in the Extended Audio Status/Control Register
(Index 2Ah) is ‘clear’, the SR[3:4,6:11] bits are always 0. When VRA is ‘set’, the SRC is en-
abled and the SR[3:4,6:11] bits are used to request data.
Valid
12
RI3
15
Slot 4
Valid
RI2
14
11
RI1
13
10
0
RI0
12
Slot 6
Valid
9
SR3 SR4
11
Slot 7
Valid
8
10
Slot 8
Valid
9
0
7
SR6 SR7 SR8 SR9 SR10 SR11
8
6
0
7
5
0
6
Slot 11
Valid
4
5
Slot 12
Valid
4
3
3
2
Reserved
2
0
CS4202
1
DS549PP2
Reserved
1
0
0