CS4202-JQZR Cirrus Logic Inc, CS4202-JQZR Datasheet - Page 45

• Manufacturer Part Number: CS4202-JQZR
• Description: IC AC97 W/Headphone Amplifier
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codec '97r

Specifications of CS4202-JQZR

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 90 / 90
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8. POWER MANAGEMENT
8.1
The CS4202 supports four reset methods, as de-
fined in the AC ’97 Specification: Cold Reset,
Warm Reset, New Warm Reset, and Register Reset.
A Cold Reset results in all AC ’97 logic (registers
included) initialized to its default state. A Warm
Reset or New Warm Reset leaves the contents of
the AC ’97 register set unaltered. A Register Reset
initializes only the AC ’97 registers to their default
states.
8.1.1
A Cold Reset is achieved by asserting RESET# for
a minimum of 1 µs after the power supply rails
have stabilized. This is done in accordance with the
minimum timing specifications in the AC ’97 Seri-
al Port Timing section on page 9. Once de-asserted,
all of the CS4202 registers will be reset to their de-
fault power-on states and the BIT_CLK and
SDATA_IN signals will be reactivated.
8.1.2
A Warm Reset allows the AC-link to be reactivated
without losing information in the CS4202 registers.
A Warm Reset is required to resume from a D3
state where the AC-link had been halted yet full
power had been maintained. A primary codec
Warm Reset is initiated when the SYNC signal is
driven high for at least 1 µs and then driven low in
the absence of the BIT_CLK clock signal. The
BIT_CLK clock will not restart until at least 2 nor-
DS549PP2
AC ’97 Reset Modes
Cold Reset
Warm Reset
hot
mal BIT_CLK clock periods (162.8 ns) after the
SYNC signal is de-asserted. A Warm Reset of the
secondary codec is recognized when the primary
codec on the AC-link resumes BIT_CLK genera-
tion. The CS4202 will wait for BIT_CLK to be sta-
ble to restore SDATA_IN activity, S/PDIF and/or
serial data port transmission on the following
frame.
8.1.3
The New Warm Reset also allows the AC-link to
be reactivated without losing information in the
registers. A New Warm Reset is required to resume
from a D3
removed. New Warm Reset is recognized by the
low-high transition of RESET# after the AC-link
has been programmed into PR4 powerdown. The
New Warm Reset functionality can be disabled by
setting the CRST bit in the Misc. Crystal Control
Register (Index 60h).
8.1.4
The last reset mode provides a Register Reset to the
CS4202. This is available only when the CS4202
AC-link is active and the Codec Ready bit is ‘set’.
The audio (including extended audio) control reg-
isters (Index 00h - 3Ah) and the vendor specific
registers (Index 5Ah - 7Ah) are reset to their de-
fault states by a write of any value to the Reset Reg-
ister (Index 00h). The modem (including GPIO)
registers (Index 3Ch - 56h) are reset to their default
states by a write of any value to the Extended Mo-
dem ID Register (Index 3Ch).
New Warm Reset
Register Reset
cold
state where AC-link power has been
CS4202
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