CS4202-JQZR Cirrus Logic Inc, CS4202-JQZR Datasheet - Page 35

• Manufacturer Part Number: CS4202-JQZR
• Description: IC AC97 W/Headphone Amplifier
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codec '97r

Specifications of CS4202-JQZR

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 90 / 90
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.19
GP[4:0]
After a Cold Reset or a modem Register Reset this register defaults to all 1’s. The upper 11 bits of this register al-
ways return ‘1’.
4.20
GS[4:0]
After a Cold Reset or a modem Register Reset this register defaults to all 0’s, specifying “non-sticky”. “Sticky” is de-
fined as edge sensitive, “non-sticky” as level sensitive. The upper 11 bits of this register always return ‘0’.
DS549PP2
Default
Default
D15
D15
1
0
GPIO Pin Polarity/Type Configuration Register (Index 4Eh)
GPIO Pin Sticky Register (Index 50h)
D14
D14
1
0
D13
D13
1
0
GPIO pin is configured as an input. The GPIO pin status of an input configured as “sticky” is
‘cleared’ by writing a ‘0’ to the corresponding bit of the GPIO Pin Status Register (Index 54h),
and by reset.
GPIO Pin Configuration. This register defines the GPIO input polarity (0 = Active Low,
1 = Active High) when a GPIO pin is configured as an input. The GP[4:0] bits define the GPIO
output type (0 = CMOS, 1 = OPEN-DRAIN) when a GPIO pin is configured as an output. The
GC[4:0] bits in the GPIO Pin Configuration Register (Index 4Ch) define the GPIO pins as in-
puts or outputs. See Table 11 for the various GPIO configurations.
FFFFh
GPIO Pin Sticky. This register defines the GPIO input type (0 = not sticky, 1 = sticky) when a
0000h
D12
D12
1
0
D11
D11
1
0
Table 11. GPIO Input/Output Configurations
GCx GPx Function
0
0
1
1
D10
D10
1
0
0
1
0
1
D9
D9
1
0
Output
Output
Input
Input
D8
D8
1
0
Active High (default)
D7
D7
1
0
Configuration
CMOS Drive
Open Drain
Active Low
D6
D6
1
0
D5
D5
1
0
GP4
GS4
D4
D4
GP3
GS3
D3
D3
GP2
GS2
D2
D2
CS4202
GP1
GS1
D1
D1
GP0
GS0
D0
D0
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