CY7C006A-20AXI Cypress Semiconductor Corp, CY7C006A-20AXI Datasheet
CY7C006A-20AXI
Specifications of CY7C006A-20AXI
CY7C006A-20AXI
Available stocks
Related parts for CY7C006A-20AXI
CY7C006A-20AXI Summary of contents
Page 1
... INT flags for port-to-port communication ■ Pin select for Master or Slave ■ Commercial temperature range ■ Available in 68-pin PLCC (CY7C006A, CY7C007A and ■ CY7C017A), 64-pin TQFP (CY7C006A), and in 80-pin TQFP (CY7C007A and CY7C016A) Pb-Free packages available ■ I/O I/O Control Control ...
Page 2
... AC Test Loads and Waveforms ....................................... 8 AC Test Loads (Applicable to –12 only) ......................... 8 Switching Characteristics ................................................ 9 Data Retention Mode ...................................................... 10 Timing .............................................................................. 10 Document Number: 38-06045 Rev. *F CY7C006A/CY7C007A CY7C016A/CY7C017A Switching Waveforms .................................................... 11 Read Cycle No. 1 (Either Port Address Access) ....... 11 Read Cycle No. 2 (Either Port CE/OE Access) ......... 11 Read Cycle No. 3 (Either Port) .................................. 11 Write Cycle No ...
Page 3
... Notes 5. This pin is I/O for CY7C017A only connect pin for 16K devices. 14 Document Number: 38-06045 Rev. *F 68-pin PLCC Top View CY7C006A (16K CY7C007A (32K CY7C017A (32K 80-pin TQFP Top View CY7C007A (32K x 8) CY7C016A (16K X 9) CY7C006A/CY7C007A CY7C016A/CY7C017A ...
Page 4
... Typical Standby Current for I (mA) (Both Ports TTL Level) SB1 Typical Standby Current for I (mA) (Both Ports CMOS Level) SB3 Note 7. See page 7 for Load Conditions. Document Number: 38-06045 Rev. *F 64-pin TQFP Top View CY7C006A (16K CY7C006A CY7C007A CY7C016A CY7C017A [7] –12 ...
Page 5
... An automatic power-down feature is controlled independently on each port by a Chip Select (CE) pin. The CY7C006A, CY7C007A and CY7C017A are available in 68-pin PLCC packages, the CY7C006A is also available in 64-pin TQFP, and the CY7C007A and CY7C016A are also available in 80-pin TQFP packages. Write Operation Data must be set up for a duration R/W in order to guarantee a valid write ...
Page 6
... The operation of the interrupts and their interaction with Busy are summarized in Table 2. Busy The CY7C006A, CY7C007A, CY7C016A and CY7C017A provide on-chip arbitration to resolve simultaneous memory location access (contention). If both ports’ CEs are asserted and an address match occurs within t of each other, the busy logic PS will determine which port has access ...
Page 7
... Industrial – Commercial 115 185 L Industrial – CY7C006A/CY7C007A CY7C016A/CY7C017A [10] ........................................–0.5V to +7.0V Ambient Temperature V CC 5V 10 +70 C CY7C006A CY7C007A CY7C016A CY7C017A –15 –20 Typ Max Min Typ Max 2.4 – – 2.4 – – – 0.4 – 0.4 2.2 – ...
Page 8
... 250 OUTPUT 1 (b) Thévenin Equivalent (Load 1) [13] 3.0 V 10% GND Capacitance (pF) (b) Load Derating Curve CY7C006A/CY7C007A CY7C016A/CY7C017A Max Unit 893 OUTPUT 347 (c) Three-State Delay (Load 2) (Used for & HZWE LZWE including scope and jig) ALL INPUT PULSES ...
Page 9
... For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 21. Test conditions used are Load 2. 22. For 15 ns industrial parts t Min. is 0.5 ns. HD Document Number: 38-06045 Rev. *F CY7C006A/CY7C007A CY7C016A/CY7C017A CY7C006A CY7C007A CY7C016A CY7C017A [15] –12 –15 Min ...
Page 10
... SEM Address Access Time SAA Data Retention Mode The CY7C006A, CY7C007A, CY7C016A, and CY7C017A are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip Enable (CE) must be held HIGH during data retention, ...
Page 11
... Address valid prior to or coincident with CE transition LOW. 30. To access RAM SEM = access semaphore Document Number: 38-06045 Rev. *F [26, 27, 28 DATA VALID [26, 29, 30] t ACE t DOE t LZOE t LZCE LZCE t ABE t ACE t LZCE , SEM = CY7C006A/CY7C007A CY7C016A/CY7C017A t OHA t HZCE t HZOE DATA VALID OHA t HZCE Page [+] Feedback ...
Page 12
... If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state. Document Number: 38-06045 Rev. *F [31, 32, 33, 34 [34] t PWE [36] t HZWE t SD [31, 32, 33, 38 SCE LOW CE or SEM PWE CY7C006A/CY7C007A CY7C016A/CY7C017A [36] t HZOE LZWE NOTE allow the I/O drivers to turn off and data HZWE SD Page [+] Feedback ...
Page 13
... SPS Document Number: 38-06045 Rev. *F [39 VALID ADRESS SCE SOP t SD DATA VALID PWE t SWRD t SOP WRITE CYCLE READ CYCLE [40, 41, 42] MATCH t SPS MATCH = CE = HIGH CY7C006A/CY7C007A CY7C016A/CY7C017A t OHA t ACE DATA VALID OUT t DOE Page [+] Feedback ...
Page 14
... Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note 43 LOW Document Number: 38-06045 Rev. *F [43 MATCH t PWE t SD VALID MATCH t BLA t WDD t PWE CY7C006A/CY7C007A CY7C016A/CY7C017A BHA t BDD t DDD VALID Page [+] Feedback ...
Page 15
... BUSY will be asserted. PS Document Number: 38-06045 Rev. *F [44] ADDRESS MATCH BLC ADDRESS MATCH BLC [44 ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA CY7C006A/CY7C007A CY7C016A/CY7C017A t BHC t BHC Page [+] Feedback ...
Page 16
... Notes 45. t depends on which enable pin ( depends on which enable pin (CE INS INR L Document Number: 38-06045 Rev WRITE 7FFF [45 [46] t INR t WC WRITE 7FFE [45 [46] t INR ) is deasserted first R asserted last. L CY7C006A/CY7C007A CY7C016A/CY7C017A t RC READ 7FFF t RC READ 7FFE Page [+] Feedback ...
Page 17
... No change. Left port has no write access to semaphore 0 1 Left port obtains semaphore token 1 1 Semaphore free 1 0 Right port has semaphore token 1 1 Semaphore free 0 1 Left port has semaphore token 1 1 Semaphore free CY7C006A/CY7C007A CY7C016A/CY7C017A Operation Right Port INT R R 0R–14R R [48 [47] L ...
Page 18
... Ordering Information 16K x 8 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 20 CY7C006A-20AC CY7C006A-20AXC CY7C006A-20AXI CY7C006A-20JXC Ordering Code Definitions 06A - Temperature Range Commercial Industrial X = Pb-free (RoHS Compliant) Package Type 64-pin TQFP J = 68-pin PLCC Speed Grade 06A = Depth: 16K 0 = Width: × Dual Port SRAM CY = Cypress Device Document Number: 38-06045 Rev ...
Page 19
... Package Diagrams 64-Lead Thin Plastic Quad Flat Pack ( 1.4 mm) A65 64-Lead Pb-Free Thin Plastic Quad Flat Pack ( 1.4 mm) A65 Document Number: 38-06045 Rev. *F CY7C006A/CY7C007A CY7C016A/CY7C017A 51-85046 *D Page [+] Feedback ...
Page 20
... Package Diagrams (continued) 80-Pin Pb-Free Thin Plastic Quad Flat Pack A80 68-Lead Plastic Leaded Chip Carrier J81 68-Lead Pb-Free Plastic Leaded Chip Carrier J81 Document Number: 38-06045 Rev. *F 80-Pin Thin Plastic Quad Flat Pack A80 CY7C006A/CY7C007A CY7C016A/CY7C017A 51-85065 *C 51-85005 *B Page [+] Feedback ...
Page 21
... Removed cross information from features section Removed I-Temp versions for both packages, since they are not valid part numbers. Included Pb-Free Logo Included package: CY7C006A-20AI Included Pb-Free packages: CY7C006A-15AXC, CY7C006A-20AXC, CY7C006A-20AXI, CY7C006A-20JXC, CY7C007A-20JXC, CY7C016A-15AXC Updated Ordering Information Updated Package Diagram Updated Ordering Information ...
Page 22
... Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-06045 Rev. *F All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised December 17, 2010 CY7C006A/CY7C007A CY7C016A/CY7C017A PSoC Solutions psoc.cypress.com/solutions PSoC 1 | ...