CY7C006A-20AXI Cypress Semiconductor Corp, CY7C006A-20AXI Datasheet - Page 5

• Manufacturer Part Number: CY7C006A-20AXI
• Description: CY7C006A-20AXI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C006A-20AXI

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 128K (16K x 8)
• Speed: 20ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2086; CY7C006A-20AXI

Document Number: 38-06045 Rev. *F
Pin Definitions
Architecture
The CY7C006A, CY7C007A, CY7C016A and CY7C017A
consist of an array of 32K/16K words of 8 bits and 32K words
of 9 bits each of dual-port RAM cells, I/O and address lines,
and control signals (CE, OE, R/W). These control pins permit
independent access for reads or writes to any location in
memory. To handle simultaneous writes/reads to the same
location, a BUSY pin is provided on each port. Two Interrupt
(INT) pins can be utilized for port-to-port communication. Two
Semaphore (SEM) control pins are used for allocating shared
resources. With the M/S pin, the devices can function as a
master (BUSY pins are outputs) or as a slave (BUSY pins are
inputs). The devices also have an automatic power-down
feature controlled by CE. Each port is provided with its own
Output Enable control (OE), which allows data to be read from
the device.
Functional Description
The CY7C006A, CY7C007A, CY7C016A, and CY7C017A are
low-power CMOS 32K × 8/9 and 16K × 8/9 dual-port static
RAMs. Various arbitration schemes are included on the
devices to handle situations when multiple processors access
the same piece of data. Two ports are provided, permitting
independent, asynchronous access for reads and writes to
any location in memory. The devices can be utilized as
standalone 8/9-bit dual-port static RAMs or multiple devices
can be combined in order to function as a 16/18-bit or wider
master/slave dual-port static RAM. An M/S pin is provided for
implementing 16/18-bit or wider memory applications without
the need for separate master and slave devices or additional
discrete logic. Application areas include interprocessor/multi-
processor designs, communications status buffering, and
dual-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE),
Read or Write Enable (R/W), and Output Enable (OE). Two
flags are provided on each port (BUSY and INT). BUSY
signals that the port is trying to access the same location
currently being accessed by the other port. The Interrupt flag
CE
R/W
OE
A
I/O
SEM
INT
BUSY
M/S
V
GND
NC
0L
CC
0L
L
L
–A
L
L
L
–I/O
L
14L
Left Port
8L
CE
R/W
OE
A
I/O
SEM
INT
BUSY
0R
0R
R
R
R
–A
R
R
–I/O
R
Right Port
14R
8R
Chip Enable
Read/Write Enable
Output Enable
Address
Data Bus Input/Output (I/O
Semaphore Enable
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
No Connect
(INT) permits communication between ports or systems by
means of a mail box. The semaphores are used to pass a flag,
or token, from one port to the other to indicate that a shared
resource is in use. The semaphore logic is comprised of eight
shared latches. Only one side can control the latch
(semaphore) at any time. Control of a semaphore indicates
that a shared resource is in use. An automatic power-down
feature is controlled independently on each port by a Chip
Select (CE) pin.
The CY7C006A, CY7C007A and CY7C017A are available in
68-pin PLCC packages, the CY7C006A is also available in
64-pin TQFP, and the CY7C007A and CY7C016A are also
available in 80-pin TQFP packages.
Write Operation
Data must be set up for a duration of t
of R/W in order to guarantee a valid write. A write operation is
controlled by either the R/W pin (see Write Cycle No. 1
waveform) or the CE pin (see Write Cycle No. 2 waveform).
Required inputs for non-contention operations are summa-
rized in
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must occur before the data is read on the output;
otherwise the data read is not deterministic. Data will be valid
on the port t
Read Operation
When reading the device, the user must assert both the OE
and CE pins. Data will be available t
OE is asserted. If the user wishes to access a semaphore flag,
then the SEM pin must be asserted instead of the CE pin, and
OE must also be asserted.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (7FFF) is the mailbox
for the right port and the second-highest memory location
Table
DDD
1.
0
–I/O
after the data is presented on the other port.
Description
7
for ×8 devices and I/O
CY7C006A/CY7C007A
CY7C016A/CY7C017A
ACE
SD
before the rising edge
after CE or t
0
–I/O
8
for ×9)
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