CY7C006A-20AXI Cypress Semiconductor Corp, CY7C006A-20AXI Datasheet - Page 9

• Manufacturer Part Number: CY7C006A-20AXI
• Description: CY7C006A-20AXI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C006A-20AXI

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 128K (16K x 8)
• Speed: 20ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2086; CY7C006A-20AXI

Switching Characteristics
Over the Operating Range
Document Number: 38-06045 Rev. *F
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Notes:
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
WC
SCE
AW
HA
SA
PWE
SD
HD
HZWE
LZWE
WDD
DDD
BLA
BHA
14. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified
15. See page 7 for Load Conditions.
16. To access RAM, CE = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire t
17. At any given temperature and voltage condition for any given device, t
18. Test conditions used are Load 3.
19. This parameter is guaranteed but not tested.
20. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
21. Test conditions used are Load 2.
22. For 15 ns industrial parts t
READ CYCLE
WRITE CYCLE
BUSY TIMING
Parameter
[19]
[19]
[16]
[22]
I
OI
[16]
[16]
[20]
[20]
[17, 18, 19]
[17, 18, 19]
[17, 18, 19]
/I
[17, 18, 19]
[18, 19]
[18, 19]
OH
and 30-pF load capacitance.
[21]
Read Cycle Time
Address to Data Valid
Output Hold From Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Write Cycle Time
CE LOW to Write End
Address Valid to Write End
Address Hold From Write End
Address Set-Up to Write Start
Write Pulse Width
Data Set-Up to Write End
Data Hold From Write End
R/W LOW to High Z
R/W HIGH to Low Z
Write Pulse to Data Delay
Write Data Valid to Read Data Valid
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
HD
[14]
Min. is 0.5 ns.
Description
HZCE
is less than t
Min
12
12
10
10
10
10
–
3
–
–
3
–
3
–
0
–
0
0
0
–
3
–
–
–
–
–12
[15]
LZCE
Max
12
12
10
10
12
10
25
20
12
12
–
–
8
–
–
–
–
–
–
–
–
–
–
–
–
and t
HZOE
Min
15
15
12
12
12
10
CY7C006A
CY7C007A
CY7C016A
CY7C017A
–
3
–
–
3
–
3
–
0
–
0
0
0
–
3
–
–
–
–
is less than t
–15
Max
15
15
10
10
10
15
10
30
25
15
15
–
–
–
–
–
–
–
–
–
–
–
–
–
–
CY7C006A/CY7C007A
CY7C016A/CY7C017A
LZOE
.
Min
SCE
20
15
15
20
15
15
–
3
–
3
–
3
–
–
0
0
0
–
3
–
–
–
–
0
–
time.
–20
Max
20
20
12
12
20
12
45
20
20
12
30
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Page 9 of 22
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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