CY7C09579V-83AXC Cypress Semiconductor Corp, CY7C09579V-83AXC Datasheet - Page 10

IC,SYNC SRAM,32KX36,CMOS,QFP,144PIN,PLASTIC

CY7C09579V-83AXC

Manufacturer Part Number
CY7C09579V-83AXC
Description
IC,SYNC SRAM,32KX36,CMOS,QFP,144PIN,PLASTIC
Manufacturer
Cypress Semiconductor Corp

Specifications of CY7C09579V-83AXC

Format - Memory
RAM
Memory Type
SRAM - Dual Port, Synchronous
Memory Size
1.152M (32K x 36)
Speed
83MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
144-LQFP
Density
1.125Mb
Access Time (max)
18ns
Sync/async
Synchronous
Architecture
SDR
Clock Freq (max)
45MHz
Operating Supply Voltage (typ)
3.3V
Address Bus
15b
Package Type
TQFP
Operating Temp Range
0C to 70C
Number Of Ports
2
Supply Current
360mA
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.465V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
144
Word Size
36b
Number Of Words
32K
Lead Free Status / RoHS Status
Lead free / RoHS compliant by exemption
Lead Free Status / RoHS Status
Lead free / RoHS compliant by exemption

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C09579V-83AXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Switching Waveforms
Read Cycle for Flow-Through Output (FT/PIPE = V
Read Cycle for Pipelined Operation (FT/PIPE = V
Notes
Document Number: 38-06054 Rev. *E
12. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
13. ADS = V
14. The output is disabled (high-impedance state) by CE=V
15. Addresses do not have to be accessed sequentially since ADS = V
Data
Address
Data
Address
B
CLK
R/W
CLK
R/W
OUT
B
OUT
CE
0-3
OE
IL
OE
CE
0-3
, CNTEN = V
t
t
t
t
t
t
SC
SW
SA
SC
SW
SA
IL
and CNTRST = V
A
A
n
n
t
t
t
t
t
t
t
HC
HW
HA
t
CH2
HC
HW
HA
CH1
t
1 Latency
CKLZ
t
CD1
t
IH
t
CYC2
CYC1
.
t
t
CKLZ
SB
t
t
t
SB
CL2
CL1
IH
A
A
n+1
following the next rising edge of the clock.
n+1
t
Q
DC
t
HB
n
t
t
CD2
IL
HB
constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
IH
IL
)
[12, 13, 14, 15]
)
[12, 13, 14, 15]
Q
A
A
n
n+2
n+2
Q
t
OHZ
n+1
t
DC
Q
t
t
t
SC
OE
SC
t
n+1
t
OLZ
OHZ
A
A
n+3
n+3
t
OLZ
Q
t
DC
n+2
t
t
HC
HC
t
CKHZ
t
OE
CY7C09569V
CY7C09579V
Q
Page 10 of 32
n+2
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