CY7C1350G-166AXI Cypress Semiconductor Corp, CY7C1350G-166AXI Datasheet

CY7C1350G-166AXI

CY7C1350G-166AXI

Manufacturer Part Number
CY7C1350G-166AXI
Description
CY7C1350G-166AXI
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C1350G-166AXI

Format - Memory
RAM
Memory Type
SRAM - Synchronous
Memory Size
4.5M (128K x 36)
Speed
166MHz
Interface
Parallel
Voltage - Supply
3.135 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C1350G-166AXI
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Cypress Semiconductor Corporation
Document #: 38-05524 Rev. *G
Features
Note:
Logic Block Diagram
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
• Pin compatible and functionally equivalent to ZBT™
• Internally self-timed output buffer control to eliminate
• Byte Write capability
• 128K x 36 common I/O architecture
• 3.3V power supply (V
• 2.5V/3.3V I/O power supply (V
• Fast clock-to-output times
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Asynchronous output enable (OE)
• Available in lead-free 100-Pin TQFP package, lead-free
• Burst Capability—linear or interleaved burst order
• “ZZ” Sleep mode option
CEN
CLK
devices
the need to use OE
— 2.6 ns (for 250-MHz device)
and non-lead-free 119-Ball BGA package
A0, A1, A
ADV/LD
MODE
BW
BW
BW
BW
C
WE
CE1
CE2
CE3
OE
ZZ
A
B
C
D
DD
)
WRITE ADDRESS
REGISTER 1
REGISTER 0
ADDRESS
DDQ
CONTROL
READ LOGIC
SLEEP
)
AND DATA COHERENCY
WRITE REGISTRY
CONTROL LOGIC
WRITE ADDRESS
ADV/LD
REGISTER 2
198 Champion Court
C
A1
A0
D1
D0
4-Mbit (128K x 36) Pipelined SRAM
BURST
LOGIC
Q1
Q0
A1'
A0'
Functional Description
The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined
Burst SRAM designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1350G is equipped with the advanced
No Bus Latency™ (NoBL™) logic required to enable consec-
utive Read/Write operations with data being transferred on
every clock cycle. This feature dramatically improves the
throughput of the SRAM, especially in systems that require
frequent Write/Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which, when deasserted, suspends operation and extends the
previous clock cycle. Maximum access delay from the clock
rise is 2.6 ns (250-MHz device)
Write operations are controlled by the four Byte Write Select
(BW
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
DRIVERS
WRITE
[A:D]
) and a Write Enable (WE) input. All writes are
San Jose
with NoBL™ Architecture
REGISTER 1
MEMORY
ARRAY
INPUT
,
E
CA 95134-1709
M
N
A
S
E
S
E
P
S
[1]
E
Revised March 20, 2010
REGISTER 0
INPUT
D
A
T
A
S
T
E
E
R
N
G
I
1
, CE
E
CY7C1350G
O
U
U
U
T
P
T
B
F
F
E
R
S
E
2
, CE
408-943-2600
3
) and an
DQs
DQP
DQP
DQP
DQP
A
B
C
D
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Related parts for CY7C1350G-166AXI

CY7C1350G-166AXI Summary of contents

Page 1

... Document #: 38-05524 Rev. *G 4-Mbit (128K x 36) Pipelined SRAM with NoBL™ Architecture Functional Description The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ ...

Page 2

... V DDQ DDQ BYTE DDQ DQP 30 D Document #: 38-05524 Rev. *G 250 MHz 200 MHz 166 MHz 2.6 2.8 3.5 325 265 240 100-Pin TQFP Pinout CY7C1350G CY7C1350G 133 MHz 100 MHz Unit 4.0 4.5 ns 225 205 DQP DDQ BYTE DDQ DDQ 60 V ...

Page 3

... Document #: 38-05524 Rev. *G 119-Ball BGA Pinout NC/18M ADV/ DQP NC/ CLK CEN DQP MODE NC/72M Description are fed to the two-bit burst counter. [1:0] to select/deselect the device select/deselect the device select/deselect the device. 2 CY7C1350G DDQ DQP DDQ DDQ DDQ DQP NC/288M NC/36M DDQ Page [+] Feedback ...

Page 4

... Burst Read Accesses The CY7C1350G has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD ...

Page 5

... OE. Burst Write Accesses The CY7C1350G has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Write operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Access section above ...

Page 6

... Table only lists a partial listing of the byte write combinations. Any combination of BW Document #: 38-05524 Rev ADV/ [ Test Conditions − 0.2V ZZ > − 0.2V ZZ > < 0.2V This parameter is sampled This parameter is sampled is valid. Appropriate write will be done on which byte write is active. X CY7C1350G OE CEN CLK L-H Tri-State L-H Tri-State L-H — Tri-State ...

Page 7

... Max, Device Deselected, All speeds ≤ 0. > V – 0.3V DDQ /2), undershoot: V (AC)> –2V (Pulse width less than t CYC IL (min.) within 200 ms. During this time V < V and CY7C1350G + 0.5V DD Ambient Temperature ( DDQ 0°C to +70°C 3.3V – 5% 2.5V – 5% +10 −40°C to +85°C DD Min ...

Page 8

... EIA/JESD51 317Ω 3.3V V OUTPUT DDQ GND 351Ω ≤ INCLUDING JIG AND (b) SCOPE R = 1667Ω 2.5V V DDQ OUTPUT GND =1538Ω ≤ INCLUDING JIG AND (b) SCOPE CY7C1350G Min. Max. Unit 105 119 BGA 100 TQFP Max. Max. Unit ...

Page 9

... V and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ = 2.5V. DDQ CY7C1350G –166 –133 –100 Max. Min. Max. Min. Max. Unit 7 ...

Page 10

... DOH CLZ D(A1) D(A2) Q(A3) D(A2+1) t OEHZ READ READ BURST Q(A3) Q(A4) READ Q(A4+1) DON’T CARE UNDEFINED is LOW. When CE is HIGH HIGH CY7C1350G OEV CHZ Q(A4) Q(A4+1) D(A5) Q(A6) t DOH t OELZ WRITE READ WRITE DESELECT D(A5) Q(A6) D(A7) is LOW HIGH ...

Page 11

... DQs are in high-Z when exiting ZZ sleep mode. Document #: 38-05524 Rev D(A1) Q(A2) Q(A3) STALL READ WRITE STALL Q(A3) D(A4) DON’T CARE UNDEFINED High-Z DON’T CARE CY7C1350G CHZ D(A4) Q(A5) NOP READ DESELECT CONTINUE Q(A5) DESELECT t ZZREC t RZZI DESELECT or READ Only Page ...

Page 12

... CY7C1350G-133AXC 51-85050 100-Pin Thin Quad Flat Pack ( 1.4 mm) Lead-Free CY7C1350G-133AXI 51-85050 100-Pin Thin Quad Flat Pack ( 1.4 mm) Lead-Free 166 CY7C1350G-166AXI 51-85050 100-Pin Thin Quad Flat Pack ( 1.4 mm) Lead-Free 200 CY7C1350G-200AXC 51-85050 100-Pin Thin Quad Flat Pack ( 1.4 mm) Lead-Free CY7C1350G-200AXI 51-85050 100-Pin Thin Quad Flat Pack ( 1.4 mm) Lead-Free Package Diagrams Document #: 38-05524 Rev ...

Page 13

... BGA ( 2.4 mm) (51-85115) ZBT is a trademark of Integrated Device Technology, Inc. NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05524 Rev. *G CY7C1350G 51-85115-*C Page [+] Feedback ...

Page 14

... Document History Page Document Title: CY7C1350G 4-Mbit (128K x 36) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05524 Orig. of REV. ECN NO. Issue Date Change Description of Change ** 224380 See ECN RKF *A 276690 See ECN VBL *B 332895 See ECN SYT *C 351194 See ECN ...

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