CY7C1350G-200AXI Cypress Semiconductor Corp, CY7C1350G-200AXI Datasheet
CY7C1350G-200AXI
Specifications of CY7C1350G-200AXI
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CY7C1350G-200AXI Summary of contents
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... Document #: 38-05524 Rev. *F 4-Mbit (128K x 36) Pipelined SRAM with NoBL™ Architecture Functional Description The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ ...
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... V DDQ DDQ BYTE DDQ DQP 30 D Document #: 38-05524 Rev. *F 250 MHz 200 MHz 166 MHz 2.6 2.8 3.5 325 265 240 100-Pin TQFP Pinout CY7C1350G CY7C1350G 133 MHz 100 MHz Unit 4.0 4.5 ns 225 205 DQP DDQ BYTE DDQ DDQ 60 V ...
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... Document #: 38-05524 Rev. *F 119-Ball BGA Pinout NC/18M ADV/ DQP NC/ CLK CEN DQP MODE NC/72M Description are fed to the two-bit burst counter. [1:0] to select/deselect the device select/deselect the device select/deselect the device. 2 CY7C1350G DDQ DQP DDQ DDQ DDQ DQP NC/288M NC/36M DDQ Page [+] Feedback ...
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... Burst Read Accesses The CY7C1350G has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD ...
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... OE. Burst Write Accesses The CY7C1350G has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Write operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Access section above ...
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... Table only lists a partial listing of the byte write combinations. Any combination of BW Document #: 38-05524 Rev ADV/ [ Test Conditions − 0.2V ZZ > − 0.2V ZZ > < 0.2V This parameter is sampled This parameter is sampled is valid. Appropriate write will be done on which byte write is active. X CY7C1350G OE CEN CLK L-H Tri-State L-H Tri-State L-H — Tri-State ...
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... Max, Device Deselected, All speeds ≤ 0. > V – 0.3V DDQ /2), undershoot: V (AC)> –2V (Pulse width less than t CYC IL (min.) within 200 ms. During this time V < V and CY7C1350G + 0.5V DD Ambient Temperature ( DDQ 0°C to +70°C 3.3V – 5% 2.5V – 5% +10 −40°C to +85°C DD Min ...
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... EIA/JESD51 317Ω 3.3V V OUTPUT DDQ GND 351Ω ≤ INCLUDING JIG AND (b) SCOPE R = 1667Ω 2.5V V DDQ OUTPUT GND =1538Ω ≤ INCLUDING JIG AND (b) SCOPE CY7C1350G Min. Max. Unit 105 119 BGA 100 TQFP Max. Max. Unit ...
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... V and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ = 2.5V. DDQ CY7C1350G –166 –133 –100 Max. Min. Max. Min. Max. Unit 7 ...
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... DOH CLZ D(A1) D(A2) D(A2+1) Q(A3) t OEHZ READ READ BURST Q(A3) Q(A4) READ Q(A4+1) DON’T CARE UNDEFINED is LOW. When CE is HIGH HIGH CY7C1350G OEV CHZ Q(A4) Q(A4+1) D(A5) Q(A6) t DOH t OELZ WRITE READ WRITE DESELECT D(A5) Q(A6) D(A7) is LOW HIGH ...
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... DQs are in high-Z when exiting ZZ sleep mode. Document #: 38-05524 Rev D(A1) Q(A2) Q(A3) STALL READ WRITE STALL Q(A3) D(A4) DON’T CARE UNDEFINED High-Z DON’T CARE CY7C1350G CHZ D(A4) Q(A5) NOP READ DESELECT CONTINUE Q(A5) DESELECT t ZZREC t RZZI DESELECT or READ Only Page [+] Feedback ...
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... CY7C1350G-166BGXI 200 CY7C1350G-200AXC 51-85050 100-Pin Thin Quad Flat Pack ( 1.4 mm) Lead-Free CY7C1350G-200BGC 51-85115 119-ball Ball Grid Array ( 2.4 mm) CY7C1350G-200BGXC CY7C1350G-200AXI 51-85050 100-Pin Thin Quad Flat Pack ( 1.4 mm) Lead-Free CY7C1350G-200BGI 51-85115 119-ball Ball Grid Array ( 2.4 mm) CY7C1350G-200BGXI 250 CY7C1350G-250AXC 51-85050 100-Pin Thin Quad Flat Pack ( 1.4 mm) Lead-Free CY7C1350G-250BGC 51-85115 119-ball Ball Grid Array ( ...
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... BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS A CY7C1350G 1.40±0.05 12°±1° SEE DETAIL (8X) ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 119-Ball BGA ( 2.4 mm) (51-85115) Ø1.00(3X) REF 0.15(4X) CY7C1350G Ø0. Ø0. Ø0.75±0.15(119X ...
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... Document History Page Document Title: CY7C1350G 4-Mbit (128K x 36) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05524 Issue Orig. of REV. ECN NO. Date Change Description of Change ** 224380 See ECN RKF *A 276690 See ECN VBL *B 332895 See ECN SYT *C 351194 See ECN ...