CY7C1350G-200AXI Cypress Semiconductor Corp, CY7C1350G-200AXI Datasheet - Page 3

• Manufacturer Part Number: CY7C1350G-200AXI
• Description: CY7C1350G-200AXI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1350G-200AXI

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 4.5M (128K x 36)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-05524 Rev. *F
Pin Configurations
Pin Definitions
A0, A1, A
BW
WE
ADV/LD
CLK
CE
CE
CE
OE
CEN
Name
1
2
3
[A:D]
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Input-Clock
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
I/O
M
A
B
C
D
G
H
K
N
R
U
E
F
J
L
P
T
(continued)
Address Inputs used to select one of the 128K address locations. Sampled at the rising edge
of the CLK. A
Byte Write Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on
the rising edge of CLK.
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
Advance/Load Input. Used to advance the on-chip address counter or load a new address. When
HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new
address can be loaded into the device for an access. After being deselected, ADV/LD should be
driven LOW in order to load a new address.
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
Output Enable, asynchronous input, active LOW. Combined with the synchronous logic block
inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE
is masked during the data portion of a write sequence, during the first clock when emerging from
a deselected state, when the device has been deselected.
Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the
SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
NC/576M
NC/144M
NC/1G
V
V
V
V
V
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
2
1
1
NC
DDQ
DDQ
DDQ
DDQ
DDQ
1
and CE
and CE
and CE
C
C
C
C
D
D
D
D
NC/72M
2
DQP
DQP
3
3
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CE
V
NC
[1:0]
to select/deselect the device.
to select/deselect the device.
to select/deselect the device.
A
2
A
A
DD
2
C
C
C
C
D
D
D
D
C
D
are fed to the two-bit burst counter.
119-Ball BGA Pinout
MODE
BW
BW
V
V
V
V
V
V
V
V
V
NC
A
A
A
A
3
SS
SS
SS
SS
SS
SS
SS
SS
SS
C
D
NC/18M
ADV/LD
NC/9M
CEN
CLK
V
CE
V
V
WE
NC
OE
NC
NC
A1
A0
4
A
DD
DD
DD
1
Description
BW
BW
V
V
V
V
V
V
V
V
V
NC
NC
5
A
A
A
A
SS
SS
SS
SS
SS
SS
SS
SS
SS
A
B
NC/36M
DQP
DQP
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CE
V
NC
6
A
A
A
DD
3
B
B
B
B
A
A
A
A
A
B
NC/288M
V
V
V
V
V
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
NC
NC
ZZ
DDQ
DDQ
DDQ
DDQ
DDQ
7
B
B
B
B
A
A
A
A
CY7C1350G
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