CY7C1363C-133AJXI Cypress Semiconductor Corp, CY7C1363C-133AJXI Datasheet
CY7C1363C-133AJXI
Specifications of CY7C1363C-133AJXI
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CY7C1363C-133AJXI Summary of contents
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... Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). The CY7C1361C/CY7C1363C operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. ...
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... DQP , BYTE WRITE REGISTER DQ DQP , BYTE BWE WRITE REGISTER GW ENABLE CE1 REGISTER CE2 CE3 OE SLEEP ZZ CONTROL Logic Block Diagram – CY7C1363C (512K x 18) ADDRESS A0,A1,A REGISTER MODE ADV CLK ADSC ADSP DQ ,DQP B B WRITE REGISTER ,DQP WRITE REGISTER BWE GW ENABLE CE 1 REGISTER ...
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... DDQ V 21 SSQ SSQ V 27 DDQ DQP 30 D Document #: 38-05541 Rev. *G CY7C1361C/CY7C1363C DQP DDQ 4 DDQ SSQ 5 SSQ SSQ 10 SSQ DDQ 11 DDQ /DNU CY7C1363C (512K x 18 DDQ 20 DDQ SSQ 21 SSQ DQP SSQ 26 SSQ DDQ 27 DDQ DQP DDQ V 76 SSQ DQP SSQ V 70 ...
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... V 20 DDQ V 21 SSQ SSQ V 27 DDQ DQP 30 D Document #: 38-05541 Rev. *G CY7C1361C/CY7C1363C 80 DQP DDQ 4 DDQ SSQ 5 SSQ SSQ 10 SSQ DDQ 11 DDQ /DNU CY7C1363C (512K x 18 DDQ 20 DDQ SSQ 21 SSQ DQP SSQ 26 SSQ DDQ 27 DDQ DQP DDQ 76 V SSQ DQP SSQ ...
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... NC/72M V U DDQ Document #: 38-05541 Rev. *G CY7C1361C (256K x 36 ADSP ADSC DQP ADV CLK BWE DQP MODE NC/72M TMS TDI TCK TDO CY7C1363C (512K x 18 ADSP ADSC ADV CLK BWE DQP MODE NC/36M A TMS TDI TCK TDO CY7C1361C/CY7C1363C DDQ A NC/512M A NC/1G ...
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... P NC NC/72M A R MODE NC/36M A Document #: 38-05541 Rev. *G Figure 4. 165-Ball FBGA (3 Chip Enable) CY7C1361C (256K x 36 BWE CLK NC/18M SS TDI A1 TDO A A0 TCK A TMS CY7C1363C (512K x 18 BWE CLK NC/18M NC SS TDI A1 TDO TCK TMS CY7C1361C/CY7C1363C ADSC ADV A NC ADSP NC/576M OE ...
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... When ADSP and ADSC are both [1:0] are also loaded into the burst counter. When ADSP and ADSC are both [1:0] and DQP s is controlled CY7C1361C/CY7C1363C [ and CE are sampled and BWE ...
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... No Connects. Not internally connected to the die. 18M, 36M, 72M, 144M, 288M, 576M, and 1G are address expansion pins and are not internally connected to the die. V /DNU Ground/DNU This pin can be connected to Ground or should be left floating. SS Document #: 38-05541 Rev. *G CY7C1361C/CY7C1363C Description . This pin is not available on TQFP packages. SS through a pull DD . This pin is DD ...
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... Maximum access delay from the clock rise ( 6.5 ns (133 MHz device). CDV The CY7C1361C/CY7C1363C supports secondary cache in systems using either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486™ processors. The linear burst sequence is suited for processors that use a linear burst sequence ...
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... ZZ recovery time ZZREC t ZZ active to sleep current ZZI t ZZ Inactive to exit sleep current RZZI Truth Table The Truth Table for CY7C1361C and CY7C1363C follows. Address Cycle Description Used Deselected Cycle, Power Down None Deselected Cycle, Power Down None Deselected Cycle, Power Down ...
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... DQP D C Write Bytes ( DQP , DQP , DQP D B Write All Bytes Write All Bytes Truth Table for Read/Write [3, 8] The Truth Table for Read/Write follows. Function (CY7C1363C) Read Read Write Byte A – (DQ and DQP ) A A Write Byte B – (DQ and DQP ) B B Write All Bytes ...
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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1361C/CY7C1363C incorporates a serial boundary scan test access port (TAP) in the BGA package only. The TQFP package does not offer this functionality. This part operates in accordance with IEEE Standard 1149.1-1900, but does not have the set of functions required for full 1149.1 compliance. These ...
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... High-Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1-mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruc- tion register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the on boundary scan register. CY7C1361C/CY7C1363C Page [+] Feedback ...
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... BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions TDIS t TDIH t TDOX DON’ UNDEFINED CY7C1361C/CY7C1363C TDOV Page [+] Feedback ...
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... Notes 9. t and t refer to the setup and hold time requirements of latching data from the boundary scan register 10. Test conditions are specified using the load in TAP AC test conditions. t Document #: 38-05541 Rev. *G [9, 10] Over the Operating Range Parameter / ns CY7C1361C/CY7C1363C Min Max Unit MHz ...
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... Defines memory type and architecture 000001 000001 Defines memory type and architecture 100110 010110 Defines width and density 00000110100 00000110100 Allows unique identification of SRAM vendor Indicates the presence register. CY7C1361C/CY7C1363C to 2.5V SS 1.25V 50Ω 50Ω 20pF O Min Max Unit 2 ...
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... Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Document #: 38-05541 Rev. *G CY7C1361C/CY7C1363C Bit Size (x 36) Bit Size (x 18 ...
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... Internal DQP Internal Document #: 38-05541 Rev. *G CY7C1363C (512K x 18) Signal Signal Bit # ball ID Name Name A0 1 CLK BWE ADSC ADSP MODE 7 G4 ADV DQP Internal Internal Internal Internal Internal Internal DQP Internal Internal Internal Internal Internal C DQP 26 Internal Internal Internal Internal ...
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... DQ 25 Internal C DQP 26 Internal Internal Internal R11 R10 P10 P11 CY7C1361C/CY7C1363C CY7C1363C (512K x 18) Signal Signal Bit # ball ID Name Name CLK BWE ADSC ADSP ADV 43 R1 MODE A 44 Internal Internal A 45 Internal Internal A 46 Internal Internal Internal 47 Internal Internal Internal 48 N1 ...
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... I DDQ < V Output Disabled I DDQ, /2), undershoot: V (AC) > –2V (Pulse width less than t CYC IL (min.) within 200ms. During this time V < V and CY7C1361C/CY7C1363C Test Description Typ Max* Unit Conditions Logical 25°C 361 394 Single-Bit Upsets Logical 25°C 0 0.01 Multi-Bit Upsets 85°C 0 0.1 ...
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... Figure 5. AC Test Loads and Waveforms R = 317Ω 3.3V V OUTPUT GND 351Ω INCLUDING JIG AND SCOPE ( 1667Ω 2.5V V DDQ OUTPUT GND 1538Ω INCLUDING JIG AND (b) SCOPE CY7C1361C/CY7C1363C Min Max 250 180 110 150 40 100 120 40 60 119 BGA 165 FBGA Unit Max. Max ...
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... Hold After CLK Rise 0.5 0.5 0.5 0.5 is the time that the power needs to be supplied above V and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ = 2.5V. DDQ CY7C1361C/CY7C1363C –100 Unit Min Max 4.0 ns 4.0 ns 6.5 8 ...
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... ADVS ADVH ADV suspends burst t CDV t OELZ t DOH Q(A2 BURST READ DON’T CARE UNDEFINED is HIGH and CE is LOW. When CE is HIGH CY7C1361C/CY7C1363C Deselect Cycle t CHZ Q( Q(A2 Burst wraps around to its initial state is HIGH LOW HIGH Page [+] Feedback ...
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... Full width write can be initiated by either GW LOW HIGH, BWE LOW and BW Document #: 38-05541 Rev. *G [22, 23] Figure 7. Write Cycle Timing ADSC extends burst WEH WES ADV suspends burst D(A2 BURST WRITE DON’T CARE UNDEFINED LOW. X CY7C1361C/CY7C1363C t ADS t ADH A3 t WES t WEH t ADVS t ADVH D( D(A3 Extended BURST WRITE Page [+] Feedback ...
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... The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC. 25 HIGH. Document #: 38-05541 Rev. *G [22, 24, 25 WES WEH OELZ D(A3) t CDV Q(A4) Q(A4+1) Single WRITE BURST READ DON’T CARE UNDEFINED CY7C1361C/CY7C1363C A5 A6 D(A5) D(A6) Q(A4+2) Q(A4+3) Back-to-Back WRITEs Page [+] Feedback ...
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... Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 27. DQs are in high-Z when exiting ZZ sleep mode. Document #: 38-05541 Rev. *G [26, 27] Figure 9. ZZ Mode Timing High-Z DON’T CARE CY7C1361C/CY7C1363C t ZZREC t RZZI DESELECT or READ Only Page [+] Feedback ...
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... CY7C1363C-133AXC CY7C1361C-133AJXC 51-85050 100-pin Thin Quad Flat Pack ( 1.4 mm) Lead-Free CY7C1363C-133AJXC CY7C1361C-133AXI 51-85050 100-pin Thin Quad Flat Pack ( 1.4 mm) Lead-Free CY7C1363C-133AJXI 51-85050 100-pin Thin Quad Flat Pack ( 1.4 mm) Lead-Free 100 CY7C1361C-100AXC 51-85050 100-pin Thin Quad Flat Pack ( 1.4 mm) Lead-Free CY7C1361C-100BGC 51-85115 119-ball Ball Grid Array ( 2.4 mm) ...
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... BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 0.20 MAX. 3. DIMENSIONS IN MILLIMETERS A CY7C1361C/CY7C1363C 1.40±0.05 12°±1° SEE DETAIL (8X) 0.20 MAX. ...
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... A1 CORNER 0.70 REF. 12.00 30° TYP. SEATING PLANE C Document #: 38-05541 Rev. *G Figure 11. 119-Ball BGA (14X22X2.4 mm) Ø1.00(3X) REF 0.15(4X) CY7C1361C/CY7C1363C Ø0. Ø0. Ø0.75±0.15(119X 1.27 3.81 7.62 14.00±0.20 51-85115-*B Page [+] Feedback ...
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... TOP VIEW PIN 1 CORNER 13.00±0.10 SEATING PLANE C Document #: 38-05541 Rev. *G Figure 12. 165-Ball FBGA (13X15X1.4 mm 0.15(4X) CY7C1361C/CY7C1363C BOTTOM VIEW PIN 1 CORNER Ø0. Ø0. -0.06 Ø0.50 (165X) +0. 1.00 5.00 10.00 13.00±0.10 NOTES : SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) PACKAGE WEIGHT : 0.475g ...
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... Document History Page Document Title: CY7C1361C/CY7C1363C 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Document Number: 38-05541 Submission REV. ECN NO. Date ** 241690 See ECN *A 278969 See ECN *B 332059 See ECN *C 377095 See ECN *D 408298 See ECN *E 433033 See ECN *F 501793 See ECN *G 2756340 08/26/2009 Document #: 38-05541 Rev ...
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... Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-05541 Rev. *G All products and company names mentioned in this document may be the trademarks of their respective holders. psoc.cypress.com clocks.cypress.com image.cypress.com Revised August 26, 2009 CY7C1361C/CY7C1363C Page [+] Feedback ...