CY7C1463AV33-133AXC Cypress Semiconductor Corp, CY7C1463AV33-133AXC Datasheet

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... × 36/2 M × 18/512 K × 72 Synchronous Flow-Through Burst SRAMs designed specifically to support unlimited true back-to-back read and write operations without the insertion of wait states. The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 is equipped with the advanced NoBL logic required to enable consecutive read and write operations with data being transferred on every clock cycle ...

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... REGISTER MODE CE CLK C CEN WRITE ADDRESS ADV/ READ LOGIC CE1 CE2 CE3 SLEEP ZZ CONTROL Logic Block Diagram – CY7C1463AV33 (2 M × 18) ADDRESS A0, A1, A REGISTER MODE CE CLK C CEN WRITE ADDRESS ADV/ READ LOGIC CE1 CE2 CE3 SLEEP ZZ CONTROL Document #: 38-05356 Rev. *I CY7C1463AV33, CY7C1465AV33 ...

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... Logic Block Diagram – CY7C1465AV33 (512 K × 72) ADDRESS A0, A1, A REGISTER MODE CE CLK C CEN WRITE ADDRESS ADV/ READ LOGIC CE1 CE2 CE3 SLEEP ZZ CONTROL Document #: 38-05356 Rev. *I CY7C1463AV33, CY7C1465AV33 BURST ADV/LD LOGIC C REGISTER WRITE REGISTRY WRITE DRIVERS AND DATA COHERENCY CONTROL LOGIC CY7C1461AV33 MEMORY E ...

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... PERFORMING A TAP RESET .................................. 14 TAP REGISTERS ...................................................... 14 TAP Instruction Set ................................................... 15 TAP Timing ...................................................................... 16 TAP AC Switching Characteristics ............................... 17 Document #: 38-05356 Rev. *I CY7C1461AV33 CY7C1463AV33, CY7C1465AV33 3.3 V TAP AC Test Conditions ....................................... 18 3.3 V TAP AC Output Load Equivalent ......................... 18 2.5 V TAP AC Test Conditions ....................................... 18 2.5 V TAP AC Output Load Equivalent ......................... 18 TAP DC Electrical Characteristics and Operating Conditions ..................................................... 18 Identification Register Definitions ...

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... Pin Configurations DQP DDQ BYTE DDQ DDQ BYTE DDQ DQP 30 D Document #: 38-05356 Rev. *I CY7C1463AV33, CY7C1465AV33 100-pin TQFP Pinout CY7C1461AV33 CY7C1461AV33 80 DQP DDQ BYTE DDQ DDQ BYTE DDQ DQP A Page [+] Feedback ...

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... Pin Configurations (continued DDQ DDQ BYTE DDQ DQP DDQ Document #: 38-05356 Rev. *I CY7C1463AV33, CY7C1465AV33 100-pin TQFP Pinout CY7C1463AV33 CY7C1461AV33 DDQ DQP DDQ BYTE DDQ DDQ Page [+] Feedback ...

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... V B DDQ DDQ DDQ N DQP DDQ P NC/144M NC/72M A R MODE A A Document #: 38-05356 Rev. *I CY7C1463AV33, CY7C1465AV33 CY7C1461AV33 (1 M × 36 CEN CLK TDI A1 TDO A A0 TCK A TMS CY7C1463AV33 (2 M × 18 CEN CLK TDI A1 TDO A A0 TCK A TMS CY7C1461AV33 ADV/ DQP SS DDQ DDQ ...

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... DDQ CLK L DQh DQh V DDQ M DQh V DQh SS N DQh V DQh DDQ P DQh DQh DQPd DQPh DDQ T DQd DQd DQd DQd NC/144M V DQd A DQd W DQd DQd TMS Document #: 38-05356 Rev. *I CY7C1463AV33, CY7C1465AV33 CY7C1465AV33 (512 K × 72 ADV/ BWS c g NC/576M NC BWS NC/ DDQ DDQ ...

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... IO Power Power Supply for IO Circuitry. DDQ Supply V Ground Ground for the Device. SS Document #: 38-05356 Rev. *I CY7C1463AV33, CY7C1465AV33 Description are fed to the two-bit burst counter. to select or deselect the device select or deselect the device select or deselect the device. 2 are placed in a tri-state condition.The outputs are automatically tri-stated during ...

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... NC /1G N/A Not Connected to the Die. Can be tied to any voltage level. Functional Overview The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 is a synchronous flow through burst SRAM designed specifically to eliminate wait states during Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the clock enable input signal (CEN) ...

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... X write cycle, regardless of the state of OE. Burst Write Accesses The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 has an on-chip burst counter that provides the ability to supply a single address and conduct up to four write operations without reasserting the address inputs. ADV/LD must be driven LOW to ...

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... Truth Table The truth table for CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 follows. Address Operation Used Deselect Cycle None Deselect Cycle None Deselect Cycle None Continue Deselect Cycle None Read Cycle (Begin Burst) External Read Cycle (Continue Burst) Next NOP/Dummy Read External (Begin Burst) Dummy Read (Continue Burst) ...

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... X = “Don't Care.” logic HIGH logic LOW. BWx = L signifies at least one byte write select is active, BWx = Valid signifies that the desired byte write selects are asserted, see truth table for details. 10. Table only lists a partial listing of the byte write combinations. Any combination of BW Document #: 38-05356 Rev. *I CY7C1463AV33, CY7C1465AV33 ...

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... This part is fully compliant with 1149.1. The TAP operates using JEDEC-standard 3.3 V and 2 logic level. The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature ...

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... TDI and TDO balls and enables the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. Document #: 38-05356 Rev. *I CY7C1463AV33, CY7C1465AV33 The IDCODE instruction is loaded into the instruction register on power up or whenever the TAP controller is supplied a test logic reset state. ...

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... Test Data-Out (TDO) Document #: 38-05356 Rev. *I CY7C1463AV33, CY7C1465AV33 during the Shift-DR state. During Update-DR, the value loaded into that shift register cell latches into the preload register. When the EXTEST instruction is entered, this bit directly controls the output Q-bus pins. Note that this bit is pre-set HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the Test-Logic-Reset state ...

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... Capture Hold after Clock Rise CH Notes 11. t and t refer to the setup and hold time requirements of latching data from the boundary scan register 12. Test conditions are specified using the load in TAP AC test Conditions. t Document #: 38-05356 Rev. *I CY7C1463AV33, CY7C1465AV33 Description / ns CY7C1461AV33 Min Max Unit 50 – ...

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... I Input Load Current X Note 13. All voltages referenced to V (GND). SS Document #: 38-05356 Rev. *I CY7C1463AV33, CY7C1465AV33 2.5 V TAP AC Test Conditions to 3.3 V Input pulse levels................................................ V SS Input rise and fall time .....................................................1 ns Input timing reference levels........................................ 1.25 V Output reference levels .............................................. .1.25 V Test load termination supply voltage ........................... 1. ...

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... Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Note 14. Bit #24 is “1” in the ID Register Definitions for both 2.5 V and 3.3 V versions of this device. Document #: 38-05356 Rev. *I CY7C1463AV33, CY7C1465AV33 CY7C1463AV33 CY7C1465AV33 (2 M × 18) (512 K × 72) ...

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... FBGA Boundary Scan Order CY7C1461AV33 (1 M × 36), CY7C1463AV33 (2 M × 18) Bit# Ball ID Bit N10 28 4 P11 P10 34 10 R10 35 11 R11 36 12 H11 37 13 N11 38 14 M11 39 15 L11 40 16 K11 41 17 J11 42 18 M10 43 19 L10 44 20 K10 45 21 ...

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... N11 61 27 N10 62 28 M11 63 29 M10 64 30 L11 65 31 L10 66 32 K11 Note 16. Bit# 138 is preset HIGH. Document #: 38-05356 Rev. *I CY7C1463AV33, CY7C1465AV33 [16] Ball ID Bit# Ball K10 74 A6 J11 75 A5 J10 76 B5 H11 77 C5 H10 78 D5 G11 79 D4 G10 80 C4 ...

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... Notes 17. Overshoot: V (AC) < 1.5 V (Pulse width less than 18 Assumes a linear ramp from Power-up DD Document #: 38-05356 Rev. *I CY7C1463AV33, CY7C1465AV33 DC Input Voltage ................................. –0 Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage......................................... > 2001 V (MIL-STD-883, Method 3015) Latch Up Current ................................................... > 200 mA Operating Range Range DD Commercial + 0.5 V Industrial – ...

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... IO Test Load OUTPUT OUTPUT Z = 50 50 1.25V T (a) Note 19. Tested initially and after any design or process change that may affect these parameters. Document #: 38-05356 Rev. *I CY7C1463AV33, CY7C1465AV33 [19] 100-pin TQFP Test Conditions Max T = 25 MHz 2.5V DDQ 5.5 ...

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... These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High Z prior to Low Z under the same system conditions. 25. This parameter is sampled and not 100% tested. Document #: 38-05356 Rev. *I CY7C1463AV33, CY7C1465AV33 Description [23, 24, 25] = 2.5 V. ...

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... W RITE D(A2+1) Notes 26. For this waveform ZZ is tied LOW. 27. When CE is LOW LOW HIGH and 28. Order of the burst sequence is determined by the status of the MODE (0 = Linear Interleaved). Burst operations are optional. Document #: 38-05356 Rev. *I CY7C1463AV33, CY7C1465AV33 [26, 27, 28] Figure 2. Read/Write Waveforms CDV t DOH ...

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... Q(A2) Notes 29. For this waveform ZZ is tied LOW. 30. When CE is LOW LOW HIGH and 31. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle. Document #: 38-05356 Rev. *I CY7C1463AV33, CY7C1465AV33 Q(A2) Q(A3) STALL ...

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... ZZ) Outputs (Q) Notes 32. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device. 33. DQs are in High Z when exiting ZZ sleep mode. Document #: 38-05356 Rev. *I CY7C1463AV33, CY7C1465AV33 [32, 33] Figure 4. ZZ Mode Timing High-Z DON’ CY7C1461AV33 ...

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... Speed Package Ordering Code (MHz) Diagram 133 CY7C1461AV33-133AXC 51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free CY7C1463AV33-133AXC CY7C1461AV33-133AXI 51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free Ordering Code Definitions CY 7C 146X A V33 - 133 XX Document #: 38-05356 Rev ...

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... Package Diagrams Figure 5. 100-pin TQFP (14 × 20 × 1.4 mm), 51-85050 Document #: 38-05356 Rev. *I CY7C1461AV33 CY7C1463AV33, CY7C1465AV33 51-85050 *D Page [+] Feedback ...

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... Package Diagrams (continued) Figure 6. 165-ball FBGA (15 × 17 × 1.4 mm), 51-85165 Document #: 38-05356 Rev. *I CY7C1461AV33 CY7C1463AV33, CY7C1465AV33 51-85165 *B Page [+] Feedback ...

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... Package Diagrams (continued) Figure 7. 209-ball FBGA (14 × 22 × 1.76 mm), 51-85167 Document #: 38-05356 Rev. *I CY7C1461AV33 CY7C1463AV33, CY7C1465AV33 Page 51-85167 *A [+] Feedback ...

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... Document History Page Document Title: CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 36-Mbit (1 M × 36/2 M × 18/512 K × 72) Flow-Through SRAM with NoBL™ Architecture Document Number: 38-05356 Orig. of REV. ECN NO. Issue Date Change ** 254911 See ECN SYT *A 300131 See ECN SYT *B 320813 See ECN SYT *C 331551 ...

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... Document History Page (continued) Document Title: CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 36-Mbit (1 M × 36/2 M × 18/512 K × 72) Flow-Through SRAM with NoBL™ Architecture Document Number: 38-05356 Orig. of REV. ECN NO. Issue Date Change *E 473650 See ECN VKN *F 1274733 See ECN VKN/AESA Corrected typo in the “NOP, STALL and DESELECT Cycles” waveform ...

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... Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-05356 Rev. *I NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All products and company names mentioned in this document may be the trademarks of their respective holders. CY7C1463AV33, CY7C1465AV33 cypress.com/go/plc Revised March 29, 2011 CY7C1461AV33 PSoC Solutions psoc ...