CY7C1463AV33-133AXC Cypress Semiconductor Corp, CY7C1463AV33-133AXC Datasheet - Page 14

• Manufacturer Part Number: CY7C1463AV33-133AXC
• Description: CY7C1463AV33-133AXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1463AV33-133AXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 36M (2M x 18)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2026

IEEE 1149.1 Serial Boundary Scan (JTAG)
The
incorporates a serial boundary scan test access port (TAP). This
part is fully compliant with 1149.1. The TAP operates using
JEDEC-standard 3.3 V and 2.5 V IO logic level.
The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 contains a
TAP controller, instruction register, boundary scan register,
bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(V
internally pulled up and may be unconnected. They may
alternately be connected to V
must be left unconnected. On power up, the device is up in a
reset state which does not interfere with the operation of the
device.
TAP Controller State Diagram
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Document #: 38-05356 Rev. *I
SS
1
0
) to prevent clocking of the device. TDI and TMS are
TEST-LOGIC
RUN-TEST/
RESET
IDLE
0
CY7C1461AV33/CY7C1463AV33/CY7C1465AV33
1
1
0
CAPTURE-DR
UPDATE-DR
PAUSE-DR
DR-SCAN
SHIFT-DR
EXIT1-DR
EXIT2-DR
1
SELECT
0
0
1
0
1
1
DD
0
through a pull up resistor. TDO
1
1
0
0
1
0
CAPTURE-IR
UPDATE-IR
PAUSE-IR
EXIT1-IR
EXIT2-IR
1
IR-SCAN
SHIFT-IR
SELECT
0
0
1
0
1
1
0
1
1
0
0
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. TDI is internally pulled
up and can be unconnected if the TAP is unused in an
application. TDI is connected to the most significant bit (MSB) of
any register (see
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending on the current state of
the TAP state machine. The output changes on the falling edge
of TCK. TDO is connected to the least significant bit (LSB) of any
register (see
TAP Controller Block Diagram
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
At power up, the TAP is reset internally to ensure that TDO
comes up in a High Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
enable data to be scanned into and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling
edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the
On power up, the instruction register is loaded with the IDCODE
instruction. It is also loaded with the IDCODE instruction if the
controller is placed in a reset state as described in the previous
section.
TMS
TCK
TDI
CY7C1463AV33, CY7C1465AV33
Selection
Circuitry
TAP Controller State
TAP Controller Block
Boundary Scan Register
Identification Register
31
x
Instruction Register
TAP CONTROLLER
30
.
Bypass Register
29
.
.
.
.
.
TAP Controller Block
.
.
Diagram).
2
2
2
1
1
1
CY7C1461AV33
0
0
0
0
Diagram).
Selection
Circuitry
Page 14 of 34
Diagram.
TDO
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