DSPIC33FJ16GP101-E/P Microchip Technology, DSPIC33FJ16GP101-E/P Datasheet
DSPIC33FJ16GP101-E/P
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... High-Performance, Ultra Low Cost © 2011 Microchip Technology Inc. 16-bit Digital Signal Controllers Preliminary Data Sheet DS70652C ...
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... Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2011, Microchip Technology Incorporated, Printed in the U ...
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... Hz for Center-Aligned mode - PWM frequency for 11-bit resolution (@ 16 MIPS) = 15.63 kHz for Edge-Aligned mode, 7.81 kHz for Center-Aligned mode © 2011 Microchip Technology Inc. dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102 Power Management: • Single supply on-chip voltage regulator • Switch between clock sources in real time • ...
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... AND dsPIC33FJ16MC101/102 Timers/Capture/Compare/PWM: • Timer/Counters three 16-bit timers: - Can pair up to make one 32-bit timer - One timer runs as Real-Time Clock with external 32.768 kHz oscillator - Programmable prescaler • Input Capture (up to three channels): - Capture on up, down, or both edges - 16-bit capture input functions - 4-deep FIFO on each capture • ...
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... AND dsPIC33FJ16MC101/102 dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102 PRODUCT FAMILIES The device names, pin counts, memory sizes, and peripheral availability of each device are listed in Table 1. The following pages show their pinout diagrams. TABLE 1: dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102 CONTROLLER FAMILIES Device dsPIC33FJ16GP101 dsPIC33FJ16GP102 dsPIC33FJ16MC101 20 16 ...
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... AND dsPIC33FJ16MC101/102 Pin Diagrams 18-Pin PDIP/SOIC PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0 PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1 PGED1/AN2/C2INA/C1INC/RP0 PGEC1/AN3/CV /CV /C2INB/C1IND/RP1 REFIN REFOUT OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 PGED3/SOSCI/RP4 PGEC3/SOSCO/T1CK/CN0/RA4 20-Pin SSOP PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0 PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1 PGED1/AN2/C2INA/C1INC/RP0 PGEC1/AN3/CV /CV /C2INB/C1IND/RP1 REFIN REFOUT OSCO/CLKO/CN29/RA3 PGED3/SOSCI/RP4 PGEC3/SOSCO/T1CK/CN0/RA4 28-Pin SPDIP/SOIC/SSOP PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0 PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1 PGED1/AN2/C2INA/C1INC/RP0 PGEC1/AN3/CV /CV /C2INB/C1IND/RP1 REFIN REFOUT AN4/C3INC/C2INC/RP2 AN5/C3IND/C2IND/RP3 ...
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... AND dsPIC33FJ16MC101/102 Pin Diagrams (Continued) 20-Pin PDIP/SOIC/SSOP PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0 PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1 PGED1/AN2/C2INA/C1INC/RP0 PGEC1/AN3/CV /CV /C2INB/C1IND/RP1 REFIN REFOUT OSCO/CLKO/CN29/RA3 PGED3/SOSCI/RP4 PGEC3/SOSCO/T1CK/CN0/RA4 28-Pin SPDIP/SOIC/SSOP PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0 PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1 PGED1/AN2/C2INA/C1INC/RP0 PGEC1/AN3/CV /CV /C2INB/C1IND/RP1 REFIN REFOUT AN4/C3INC/C2INC/RP2 AN5/C3IND/C2IND/RP3 OSCO/CLKO/CN29/RA3 PGED3/SOSCI/RP4 PGEC3/SOSCO/T1CK/CN0/RA4 (2) FLTB1 /ASDA1/RP5 Note 1: The RPn pins can be used by any remappable peripheral. See peripherals ...
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... AND dsPIC33FJ16MC101/102 Pin Diagrams (Continued) (2) 28-Pin QFN PGED1/AN2/C2INA/C1INC/RP0 PGEC1/AN3/CV /CV /C2INB/C1IND/RP1 REFIN REFOUT AN4/C3INC/C2INC/RP2 AN5/C3IND/C2IND/RP3 OSCO/CLKO/CN29/RA3 Note 1: The RPn pins can be used by any remappable peripheral. See peripherals. 2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to V externally ...
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... AND dsPIC33FJ16MC101/102 Pin Diagrams (Continued) (2) 28-Pin QFN PGED1/AN2/C2INA/C1INC/RP0 PGEC1/AN3/CV /CV /C2INB/C1IND/RP1 REFIN REFOUT AN4/C3INC/C2INC/RP2 AN5/C3IND/C2IND/RP3 OSCO/CLKO/CN29/RA3 Note 1: The RPn pins can be used by any remappable peripheral. See peripherals. 2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to V externally ...
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... AND dsPIC33FJ16MC101/102 Pin Diagrams (Continued) 36-Pin TLA PGED1/AN2/C2INA/C1INC/RP0 PGEC1/AN3/CV /CV /C2INB/C1IND/RP1 REFIN REFOUT AN4/C3INC/C2INC/RP2 AN5/C3IND/C2IND/RP3 OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 PGED3/SOSCI/RP4 Note 1: The RPn pins can be used by any remappable peripheral. See peripherals. 2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to V externally ...
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... AND dsPIC33FJ16MC101/102 Pin Diagrams (Continued) 36-Pin TLA PGED1/AN2/C2INA/C1INC/RP0 PGEC1/AN3/CV /CV /C2INB/C1IND/RP1 REFIN REFOUT AN4/C3INC/C2INC/RP2 AN5/C3IND/C2IND/RP3 OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 PGED3/SOSCI/RP4 Note 1: The RPn pins can be used by any remappable peripheral. See peripherals. 2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to V externally ...
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... AND dsPIC33FJ16MC101/102 Table of Contents dsPIC33FJ16GP101/102 and dsPIC33FJ16MC101/102 Product Families ........................................................................................... 5 1.0 Device Overview ........................................................................................................................................................................ 15 2.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers .......................................................................................... 21 3.0 CPU............................................................................................................................................................................................ 25 4.0 Memory Organization ................................................................................................................................................................. 37 5.0 Flash Program Memory .............................................................................................................................................................. 65 6.0 Resets ....................................................................................................................................................................................... 69 7.0 Interrupt Controller ..................................................................................................................................................................... 77 8.0 Oscillator Configuration ............................................................................................................................................................ 107 9 ...
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... AND dsPIC33FJ16MC101/102 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. ...
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... AND dsPIC33FJ16MC101/102 NOTES: DS70652C-page 14 Preliminary © 2011 Microchip Technology Inc. ...
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... Digital Signal Processor (DSP) functionality with a high-performance, 16-bit microcontroller (MCU) architecture. Figure 1-1 shows a general block diagram of the core and peripheral modules in the dsPIC33FJ16GP101/ 102 and dsPIC33FJ16MC101/102 family of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams. ...
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... AND dsPIC33FJ16MC101/102 FIGURE 1-1: dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102 BLOCK DIAGRAM PSV and Table Data Access Control Block Interrupt Controller 8 23 PCU PCH PCL 23 Program Counter Stack Control Logic 23 Address Latch Program Memory Data Latch 24 Instruction Decode and Control Control Signals to Various Blocks ...
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... AND dsPIC33FJ16MC101/102 TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Buffer Pin Name PPS Type Type AN0-AN5 I Analog No CLKI I ST/ No CLKO O CMOS No — OSC1 I ST/ No CMOS OSC2 I/O — No SOSCI I ST/ No SOSCO O CMOS No — CN0-CN7 CN11-CN16 ST No CN21-CN24 ST No CN27 ST No CN29-CN30 ...
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... AND dsPIC33FJ16MC101/102 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name PPS Type Type (1,3) FLTA1 (2,3) FLTB1 PWM1L1 O — No PWM1H1 O — No PWM1L2 O — No PWM1H2 O — No PWM1L3 O — No PWM1H3 O — No RTCC O Digital No CTPLS O Digital Yes CTED1 I Digital No CTED2 I Digital ...
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... AND dsPIC33FJ16MC101/102 1.1 Referenced Sources This device data sheet is based on the following individual chapters of the “dsPIC33F/PIC24H Family Reference Manual”. These documents should be considered as the primary reference for the operation of a particular module or device feature. Note: To access the documents listed below, ...
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... AND dsPIC33FJ16MC101/102 NOTES: DS70652C-page 20 Preliminary © 2011 Microchip Technology Inc. ...
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... Basic Connection Requirements Getting started with the dsPIC33FJ16GP101/102 and dsPIC33FJ16MC101/102 family of 16-bit Digital Signal Controllers (DSCs) requires attention to a minimal set of device pin connections before proceeding with development. The following is a list of pin names, which must always be connected: • ...
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... AND dsPIC33FJ16MC101/102 FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION 10 µ Tantalum R R1 MCLR C dsPIC33F 0.1 µF Ceramic 0.1 µF 10 Ω Ceramic 2.2.1 TANK CAPACITORS On boards with power traces running longer than six inches in length suggested to use a tank capacitor for integrated circuits including DSCs to supply a local power source ...
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... AND dsPIC33FJ16MC101/102 2.5 ICSP Pins The PGECx and PGEDx pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging pur- poses recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is ...
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... AND dsPIC33FJ16MC101/102 2.7 Oscillator Value Conditions on Device Start-up If the PLL of the target device is enabled and configured for the device start-up oscillator, the maximum oscillator source frequency must be limited to 4 MHz < F < 8 MHz (for MSPLL mode MHz < < 8 MHz (for ECPLL mode) to comply with device IN PLL start-up conditions ...
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... As a result, three parameter instructions can be supported, allowing operations to be executed in a single cycle. © 2011 Microchip Technology Inc. A block diagram of the CPU is shown in the programmer’s model for the dsPIC33FJ16GP101/ 102 and dsPIC33FJ16MC101/102 is shown in Figure 3-2. family of 3 ...
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... FIGURE 3-1: dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102 CPU CORE BLOCK DIAGRAM PSV and Table Data Access Control Block Interrupt ...
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... AND dsPIC33FJ16MC101/102 FIGURE 3-2: dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102 PROGRAMMER’S MODEL DSP Operand Registers DSP Address Registers AD39 DSP ACCA Accumulators ACCB PC22 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG OAB SAB DA SRH © 2011 Microchip Technology Inc. D15 D0 W0/WREG ...
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... AND dsPIC33FJ16MC101/102 3.4 CPU Control Registers REGISTER 3-1: SR: CPU STATUS REGISTER R-0 R-0 R/C bit 15 (3) (3) R/W-0 R/W-0 R/W-0 (2) IPL<2:0> bit 7 Legend Clear only bit R = Readable bit S = Set only bit W = Writable bit ‘1’ = Bit is set ‘0’ = Bit is cleared ...
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... AND dsPIC33FJ16MC101/102 REGISTER 3-1: SR: CPU STATUS REGISTER (CONTINUED) bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits 111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) ...
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... AND dsPIC33FJ16MC101/102 REGISTER 3-2: CORCON: CORE CONTROL REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-1 SATA SATB SATDW bit 7 Legend Clear only bit R = Readable bit W = Writable bit 0’ = Bit is cleared ‘x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ ...
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... AND dsPIC33FJ16MC101/102 3.5 Arithmetic Logic Unit (ALU) The dsPIC33FJ16GP101/102 dsPIC33FJ16MC101/102 ALU is 16 bits wide and is capable of addition, subtraction, bit shifts, and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. Depending on the operation, the ALU can affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV), and Digit Carry (DC) Status bits in the SR register ...
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... AND dsPIC33FJ16MC101/102 FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In DS70652C-page 32 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Preliminary Round u Logic Zero Backfill © 2011 Microchip Technology Inc. ...
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... AND dsPIC33FJ16MC101/102 3.6.1 MULTIPLIER The 17-bit x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value ...
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... AND dsPIC33FJ16MC101/102 The SA and SB bits are modified each time data passes through the adder/subtracter, but can only be cleared by the user application. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled) ...
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... AND dsPIC33FJ16MC101/102 3.6.3.1 Round Logic The round logic is a combinational block that performs a conventional (biased) or convergent (unbiased) round function during an accumulator write (store). The Round mode is determined by the state of the RND bit in the CORCON register. It generates a 16-bit, 1.15 data value that is passed to the data space write saturation logic ...
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... AND dsPIC33FJ16MC101/102 NOTES: DS70652C-page 36 Preliminary © 2011 Microchip Technology Inc. ...
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... The exception is the use of TBLRD/TBLWT operations, which use TBLPAG<7> to permit access to the Configuration bits and Device ID and sections of the configuration memory space. The memory map for the dsPIC33FJ16GP101/102 and dsPIC33FJ16MC101/102 family of devices is shown in Figure 4-1. 0x000000 GOTO Instruction ...
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... AND dsPIC33FJ16MC101/102 4.1.1 PROGRAM MEMORY ORGANIZATION The program memory space is organized in word- addressable blocks. Although it is treated as 24 bits wide more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. ...
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... AND dsPIC33FJ16MC101/102 4.2 Data Address Space The dsPIC33FJ16GP101/102 dsPIC33FJ16MC101/102 CPU has a separate 16-bit- wide data memory space. The data space is accessed using separate Address Generation Units (AGUs) for read and write operations. The data memory maps is shown in Figure 4-3. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space ...
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... AND dsPIC33FJ16MC101/102 FIGURE 4-3: DATA MEMORY MAP FOR dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/ 102 DEVICES WITH 1 KB RAM MSB Address 0x0001 2 Kbyte SFR Space 0x07FF 0x0801 0x09FF 0x0A01 1 Kbyte SRAM Space 0x0BFF 0x0C01 0x1FFF 0x2001 0x8001 Optionally Mapped into Program Memory 0xFFFF ...
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... AND dsPIC33FJ16MC101/102 4.2.5 X AND Y DATA SPACES The core has two data spaces, X and Y. These data spaces can be considered either separate (for some DSP instructions one unified linear address range (for MCU instructions). The data spaces are accessed using two Address Generation Units (AGUs) and separate data paths ...
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TABLE 4-1: CPU CORE REGISTERS MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 0016 ...
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TABLE 4-1: CPU CORE REGISTERS MAP (CONTINUED) SFR SFR Name Bit 15 Bit 14 Bit 13 Addr XMODSRT 0048 XMODEND 004A YMODSRT 004C YMODEND 004E XBREV 0050 BREN DISICNT 0052 — — Legend unknown value on Reset, — ...
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... CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CNPU2 006A — CN30PUE CN29PUE — Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-3: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ16GP101 DEVICES SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr CNEN1 — ...
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TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — AD1IF U1TXIF IFS1 0086 — ...
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TABLE 4-6: TIMER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON ...
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TABLE 4-9: 6-OUTPUT PWM1 REGISTER MAP FOR dsPIC33FJ116MC10X DEVICES SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 P1TCON 01C0 PTEN — PTSIDL — P1TMR 01C2 PTDIR P1TPER 01C4 — P1SECMP 01C6 SEVTDIR PWM1CON1 01C8 — — — ...
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TABLE 4-11: UART1 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr U1MODE 0220 UARTEN — USIDL IREN U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — U1TXREG 0224 — — — — U1RXREG 0226 — — — ...
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TABLE 4-13: ADC1 REGISTER MAP FOR dsPIC33FJ16GP102 AND dsPIC33FJ16MC102 DEVICES File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 ...
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... TABLE 4-14: ADC1 REGISTER MAP FOR dsPIC33FJ16GP101 AND dsPIC33FJ16MC101 DEVICES File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 0300 ADC1BUF0 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ADC1BUFB 0316 ...
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TABLE 4-15: CTMU REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 CTMUCON1 033A CTMUEN — CTMUSIDL TGEN CTMUCON2 033C EDG2MOD EDG1POL EDG1SEL<3:0> CTMUICON 033E ITRIM<5:0> Legend unknown value on Reset, — = unimplemented, ...
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TABLE 4-18: COMPARATOR REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 CMSTAT 0650 CMSIDL — — CVRCON 0652 — — — CM1CON 0654 CON COE CPOL CM1MSKSRC 0656 — — — CM1MSKCON 0658 HLMS — ...
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... RPOR7 06CE — — — Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-21: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ16GP101 DEVICES File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RPOR0 06C0 — ...
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... LATB13 LATB12 ODCB 02CE ODCB15 ODCB14 ODCB13 ODCB12 Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal TABLE 4-26: PORTB REGISTER MAP FOR dsPIC33FJ16GP101 DEVICES File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISB — — 02C8 ...
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TABLE 4-27: SYSTEM CONTROL REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 RCON 0740 TRAPR IOPUWR — — OSCCON 0742 — COSC<2:0> CLKDIV 0744 ROI DOZE<2:0> OSCTUN 0748 — — — — Legend ...
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... AND dsPIC33FJ16MC101/102 4.2.6 SOFTWARE STACK In addition to its use as a working register, the W15 register in the dsPIC33FJ16GP101/102 dsPIC33FJ16MC101/102 devices is also used as a software Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower to higher addresses. It pre-decrements for stack ...
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... AND dsPIC33FJ16MC101/102 TABLE 4-30: FUNDAMENTAL ADDRESSING MODES SUPPORTED Addressing Mode File Register Direct Register Direct Register Indirect Register Indirect Post-Modified Register Indirect Pre-Modified Register Indirect with Register Offset (Register Indexed) Register Indirect with Literal Offset 4.3.3 MOVE AND ACCUMULATOR INSTRUCTIONS ...
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... AND dsPIC33FJ16MC101/102 4.4 Modulo Addressing Modulo Addressing mode is a method of providing an automated means to support circular data buffers using hardware. The objective is to remove the need for software to perform data address boundary checks when executing tightly looped code typical in many DSP algorithms. ...
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... AND dsPIC33FJ16MC101/102 4.4.3 MODULO ADDRESSING APPLICABILITY Modulo Addressing can be applied to the Effective Address (EA) calculation associated with any W register. Address boundaries check for addresses equal to: • The upper boundary addresses for incrementing buffers • The lower boundary addresses for decrementing buffers ...
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... AND dsPIC33FJ16MC101/102 FIGURE 4-6: BIT-REVERSED ADDRESS EXAMPLE b15 b14 b13 b12 b11 b10 b9 b8 b15 b14 b13 b12 b11 b10 b9 b8 TABLE 4-31: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address DS70652C-page 60 Sequential Address Bit Locations Swapped Left-to-Right Around Center of Binary Value ...
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... Harvard scheme, mean- ing that data can also be present in the program space. To use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces. Aside from normal execution, the dsPIC33FJ16GP101/ 102 and dsPIC33FJ16MC101/102 provides two methods by which program space can be accessed during operation: • ...
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... AND dsPIC33FJ16MC101/102 FIGURE 4-7: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION (1) Program Counter (2) Table Operations (1) Program Space Visibility (Remapping) User/Configuration Space Select Note 1: The Least Significant bit of program space addresses is always fixed as ‘0’ to maintain word alignment of data in the program and data spaces. ...
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... AND dsPIC33FJ16MC101/102 4.6.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data ...
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... AND dsPIC33FJ16MC101/102 4.6.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This option provides transparent access to stored constant data from the data space without the need to use special instructions (such as TBLRDL and TBLRDH) ...
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... AND dsPIC33FJ16MC101/102 5.0 FLASH PROGRAM MEMORY Note 1: This data sheet summarizes the features of the dsPIC33FJ16GP101/102 dsPIC33FJ16MC101/102 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 5. “Flash Programming” (DS70191) “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www ...
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... AND dsPIC33FJ16MC101/102 5.2 RTSP Operation The dsPIC33FJ16GP101/102 dsPIC33FJ16MC101/102 Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user application to erase a page of memory, which consists of eight rows (512 instructions); and to program one word. shows typical erase and programming times. The 8- row erase pages are edge-aligned from the beginning of program memory, on boundaries of 1536 bytes ...
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... AND dsPIC33FJ16MC101/102 REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER (1) (1) R/SO-0 R/W-0 R/W-0 WR WREN WRERR bit 15 (1) U-0 R/W-0 U-0 — ERASE bit 7 Legend Settable only bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 WR: Write Control bit 1 = Initiates a Flash memory program or erase operation ...
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... AND dsPIC33FJ16MC101/102 REGISTER 5-2: NVMKEY: NONVOLATILE MEMORY KEY REGISTER U-0 U-0 U-0 — — — bit 15 W-0 W-0 W-0 bit 7 Legend Settable only bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-8 Unimplemented: Read as ‘0’ ...
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... AND dsPIC33FJ16MC101/102 6.0 RESETS Note 1: This data sheet summarizes the features of the dsPIC33FJ16GP101/102 and dsPIC33FJ16MC101/102 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 8. “Reset” (DS70192) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www ...
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... AND dsPIC33FJ16MC101/102 REGISTER 6-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-0 U-0 TRAPR IOPUWR — bit 15 R/W-0 R/W-0 R/W-0 EXTR SWR SWDTEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TRAPR: Trap Reset Flag bit Trap Conflict Reset has occurred ...
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... AND dsPIC33FJ16MC101/102 REGISTER 6-1: RCON: RESET CONTROL REGISTER bit 1 BOR: Brown-out Reset Flag bit Brown-out Reset has occurred Brown-out Reset has not occurred bit 0 POR: Power-on Reset Flag bit Power-on Reset has occurred Power-on Reset has not occurred Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset ...
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... AND dsPIC33FJ16MC101/102 6.1 System Reset The dsPIC33FJ16GP101/102 and dsPIC33FJ16MC101/ 102 family of devices have two types of Reset: • Cold Reset • Warm Reset A cold Reset is the result of a POR or a BOR cold Reset, the FNOSC configuration bits in the FOSC device configuration register selects the device clock source ...
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... AND dsPIC33FJ16MC101/102 FIGURE 6-2: SYSTEM RESET TIMING V POR POR 1 POR 2 BOR SYSRST Oscillator Clock FSCM Device Status 1. POR: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active until V V threshold and the delay T POR POR 2 ...
Page 74
... AND dsPIC33FJ16MC101/102 6.2 POR A POR circuit ensures the device is reset from power- on. The POR circuit is active until V V threshold and the delay T has elapsed. The POR POR delay T ensures the internal device bias circuits POR become stable. The device supply voltage characteristics must meet the specified starting voltage and rise rate require- ments to generate the POR ...
Page 75
... AND dsPIC33FJ16MC101/102 6.4 External Reset (EXTR) The external Reset is generated by driving the MCLR pin low. The MCLR pin is a Schmitt trigger input with an additional glitch filter. Reset pulses that are longer than the minimum pulse width will generate a Reset. Refer to Section 26.0 “ ...
Page 76
... AND dsPIC33FJ16MC101/102 6.9.2 UNINITIALIZED W REGISTER RESET Any attempts to use the uninitialized W register as an address pointer will Reset the device. The W register array (with the exception of W15) is cleared during all Resets and is considered uninitialized until written to. 6.9.3 SECURITY RESET If a Program Flow Change (PFC) or Vector Flow ...
Page 77
... The Interrupt Controller reduces the numerous periph- eral interrupt request signals to a single interrupt request signal to the dsPIC33FJ16GP101/102 and dsPIC33FJ16MC101/102 CPU. It has the following features: • eight processor exceptions and software traps • ...
Page 78
... AND dsPIC33FJ16MC101/102 FIGURE 7-1: dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102 INTERRUPT VECTOR TABLE Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 ...
Page 79
... AND dsPIC33FJ16MC101/102 TABLE 7-1: INTERRUPT VECTORS Interrupt Vector Request (IRQ) IVT Address Number Number 8 0 0x000014 9 1 0x000016 10 2 0x000018 11 3 0x00001A 12 4 0x00001C 13 5 0x00001E 14 6 0x000020 15 7 0x000022 16 8 0x000024 17 9 0x000026 18 10 0x000028 19 11 0x00002A 20 12 0x00002C ...
Page 80
... AND dsPIC33FJ16MC101/102 TABLE 7-2: TRAP VECTORS Vector Number 7.3 Interrupt Control and Status Registers The dsPIC33FJ16GP101/102 dsPIC33FJ16MC101/102 devices implement a total of 22 registers for the interrupt controller: • INTCON1 • INTCON2 • IFSx • IECx • IPCx • INTTREG 7.3.1 INTCON1 AND INTCON2 Global interrupt control functions are controlled from INTCON1 and INTCON2 ...
Page 81
... AND dsPIC33FJ16MC101/102 REGISTER 7-1: SR: CPU STATUS REGISTER R-0 R-0 R/C bit 15 (3) (3) R/W-0 R/W-0 R/W-0 (2) (2) IPL2 IPL1 IPL0 bit 7 Legend Clear only bit R = Readable bit S = Set only bit W = Writable bit ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 IPL< ...
Page 82
... AND dsPIC33FJ16MC101/102 REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 NSTDIS OVAERR OVBERR bit 15 R/W-0 R/W-0 U-0 SFTACERR DIV0ERR — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled ...
Page 83
... AND dsPIC33FJ16MC101/102 REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED) bit 2 STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘ ...
Page 84
... AND dsPIC33FJ16MC101/102 REGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 R-0 U-0 ALTIVT DISI — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit ...
Page 85
... AND dsPIC33FJ16MC101/102 REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 U-0 R/W-0 — — AD1IF bit 15 R/W-0 R/W-0 R/W-0 T2IF OC2IF IC2IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 86
... AND dsPIC33FJ16MC101/102 REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred ...
Page 87
... AND dsPIC33FJ16MC101/102 REGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 U-0 U-0 R/W-0 — — INT2IF bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 88
... AND dsPIC33FJ16MC101/102 REGISTER 7-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-0 — — IC3IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ ...
Page 89
... AND dsPIC33FJ16MC101/102 REGISTER 7-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 R/W-0 — — CTMUIF bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 90
... AND dsPIC33FJ16MC101/102 REGISTER 7-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 U-0 R/W-0 — — AD1IE bit 15 R/W-0 R/W-0 R/W-0 T2IE OC2IE IC2IE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 91
... AND dsPIC33FJ16MC101/102 REGISTER 7-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2011 Microchip Technology Inc. ...
Page 92
... AND dsPIC33FJ16MC101/102 REGISTER 7-11: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 U-0 U-0 R/W-0 — — INT2IE bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 93
... AND dsPIC33FJ16MC101/102 REGISTER 7-12: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-0 — — IC3IE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ ...
Page 94
... AND dsPIC33FJ16MC101/102 REGISTER 7-14: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 U-0 R/W-0 — — CTMUIE bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 95
... AND dsPIC33FJ16MC101/102 REGISTER 7-15: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 — T1IP<2:0> bit 15 U-0 R/W-1 R/W-0 — IC1IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
Page 96
... AND dsPIC33FJ16MC101/102 REGISTER 7-16: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 — T2IP<2:0> bit 15 U-0 R/W-1 R/W-0 — IC2IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP<2:0>: Timer2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
Page 97
... AND dsPIC33FJ16MC101/102 REGISTER 7-17: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 — U1RXIP<2:0> bit 15 U-0 R/W-1 R/W-0 — SPI1EIP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
Page 98
... AND dsPIC33FJ16MC101/102 REGISTER 7-18: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — AD1IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 AD1IP< ...
Page 99
... AND dsPIC33FJ16MC101/102 REGISTER 7-19: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 — CNIP<2:0> bit 15 U-0 R/W-1 R/W-0 — MI2C1IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNIP<2:0>: Change Notification Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
Page 100
... AND dsPIC33FJ16MC101/102 REGISTER 7-20: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-3 Unimplemented: Read as ‘0’ ...
Page 101
... AND dsPIC33FJ16MC101/102 REGISTER 7-22: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — IC3IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 IC3IP< ...
Page 102
... AND dsPIC33FJ16MC101/102 REGISTER 7-24: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15 U-0 R/W-1 R/W-0 — FLTA1IP<2:0> bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 FLTA1IP< ...
Page 103
... AND dsPIC33FJ16MC101/102 REGISTER 7-25: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — U1EIP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 U1EIP< ...
Page 104
... AND dsPIC33FJ16MC101/102 REGISTER 7-26: IPC19: INTERRUPT PRIORITY CONTROL REGISTER 19 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — CTMUIP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 CTMUIP< ...
Page 105
... AND dsPIC33FJ16MC101/102 REGISTER 7-27: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER U-0 U-0 U-0 — — — bit 15 U-0 R-0 R-0 — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 ILR< ...
Page 106
... AND dsPIC33FJ16MC101/102 7.4 Interrupt Setup Procedures 7.4.1 INITIALIZATION To configure an interrupt source at initialization: 1. Set the NSTDIS bit (INTCON1<15>) if nested interrupts are not desired. 2. Select the user-assigned priority level for the interrupt source by writing the control bits into the appropriate IPCx register. The priority level will depend on the specific application and type of interrupt source ...
Page 107
... DOZE mode used with a doze ratio of 1:2 or lower. © 2011 Microchip Technology Inc. The oscillator system for dsPIC33FJ16GP101/102 and dsPIC33FJ16MC101/102 devices provides: • External and internal oscillator options as clock sources • An on-chip 4x Phase-Locked Loop (PLL) to scale ...
Page 108
... The output of the oscillator (or the output of the PLL if a PLL mode has been selected) F generate the device instruction clock (F peripheral clock time base (F operating speed of the device, and speeds MHz are supported by the dsPIC33FJ16GP101/102 and dsPIC33FJ16MC101/102 architecture. Instruction execution speed or device operating frequency, F EQUATION 8-1: ...
Page 109
... AND dsPIC33FJ16MC101/102 8.1.3 PLL CONFIGURATION The primary oscillator and internal FRC oscillator can optionally use an on-chip 4x PLL to obtain higher speeds of operation. For example, suppose a 8 MHz crystal is being used with the selected oscillator mode of MS with PLL. This provides a Fosc of 8 MHz * MHz. The resultant device operating speed is 32 MIPS ...
Page 110
... AND dsPIC33FJ16MC101/102 REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER U-0 R-0 R-0 — COSC<2:0> bit 15 R/W-0 R/W-0 R-0 CLKLOCK IOLOCK LOCK bit 7 Legend Value set from Configuration bits on POR R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ ...
Page 111
... AND dsPIC33FJ16MC101/102 REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER bit 1 LPOSCEN: Secondary (LP) Oscillator Enable bit 1 = Enable secondary oscillator 0 = Disable secondary oscillator bit 0 OSWEN: Oscillator Switch Enable bit 1 = Request oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete Note 1: Writes to this register require an unlock sequence. Refer to Section 52. “Oscillator (Part VI)” (DS70644) in the “ ...
Page 112
... AND dsPIC33FJ16MC101/102 REGISTER 8-2: CLKDIV: CLOCK DIVISOR REGISTER R/W-0 R/W-0 R/W-1 ROI DOZE<2:0> bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ROI: Recover on Interrupt bit 1 = Interrupts will clear the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:1 ...
Page 113
... AND dsPIC33FJ16MC101/102 REGISTER 8-3: OSCTUN: FRC OSCILLATOR TUNING REGISTER U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-0 — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN< ...
Page 114
... Clock Switching Operation Applications are free to switch among any of the four clock sources (Primary, LP, FRC, and LPRC) under software control at any time. To limit the possible side effects of this flexibility, dsPIC33FJ16GP101/102 and dsPIC33FJ16MC101/102 devices have a safeguard lock built into the switch process. Note: ...
Page 115
... AND dsPIC33FJ16MC101/102 9.0 POWER-SAVING FEATURES Note 1: This data sheet summarizes the features of the dsPIC33FJ16GP101/102 and dsPIC33FJ16MC101/102 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 9. “Watchdog Timer and Power-Saving (DS70196) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www ...
Page 116
... AND dsPIC33FJ16MC101/102 9.2.2 IDLE MODE The following occur in Idle mode: • The CPU stops executing instructions • The WDT is automatically cleared • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 9 ...
Page 117
... AND dsPIC33FJ16MC101/102 REGISTER 9-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 U-0 U-0 R/W-0 — — T3MD bit 15 R/W-0 U-0 R/W-0 I2C1MD — U1MD bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 118
... AND dsPIC33FJ16MC101/102 REGISTER 9-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-11 Unimplemented: Read as ‘0’ ...
Page 119
... AND dsPIC33FJ16MC101/102 REGISTER 9-3: PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-11 Unimplemented: Read as ‘0’ ...
Page 120
... AND dsPIC33FJ16MC101/102 NOTES: DS70652C-page 120 Preliminary © 2011 Microchip Technology Inc. ...
Page 121
... AND dsPIC33FJ16MC101/102 10.0 I/O PORTS Note 1: This data sheet summarizes the features of the dsPIC33FJ16GP101/102 and dsPIC33FJ16MC101/102 devices not intended compre- hensive reference source. To comple- ment the information in this data sheet, refer to Section 10. (DS70193) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www ...
Page 122
... AND dsPIC33FJ16MC101/102 10.1.1 OPEN-DRAIN CONFIGURATION In addition to the PORT, LAT, and TRIS registers for data control, some port pins can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output ...
Page 123
... AND dsPIC33FJ16MC101/102 10.4 Peripheral Pin Select Peripheral pin select configuration enables peripheral set selection and placement on a wide range of I/O pins. By increasing the pinout options available on a particular device, programmers can better tailor the microcontroller to their entire application, rather than trimming the application to fit the device ...
Page 124
... AND dsPIC33FJ16MC101/102 TABLE 10-1: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION) Input Name External Interrupt 1 External Interrupt 2 Timer2 External Clock Timer3 External Clock Input Capture 1 Input Capture 2 Input Capture 3 Output Compare Fault A UART1 Receive UART1 Clear To Send SPI1 Slave Select Input Note 1: Unless otherwise noted, all inputs use the Schmitt input buffers ...
Page 125
... AND dsPIC33FJ16MC101/102 TABLE 10-2: OUTPUT SELECTION FOR REMAPPABLE PIN (RPn) Function RPnR<4:0> NULL C1OUT C2OUT U1TX U1RTS SS1 OC1 OC2 CTPLS C3OUT 10.4.3 CONTROLLING CONFIGURATION CHANGES Because peripheral remapping can be changed during run time, some restrictions on peripheral remapping are needed to prevent accidental configuration changes. ...
Page 126
... AND dsPIC33FJ16MC101/102 REGISTER 10-1: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 127
... AND dsPIC33FJ16MC101/102 REGISTER 10-2: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-5 Unimplemented: Read as ‘0’ ...
Page 128
... AND dsPIC33FJ16MC101/102 REGISTER 10-3: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 129
... AND dsPIC33FJ16MC101/102 REGISTER 10-4: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 130
... AND dsPIC33FJ16MC101/102 REGISTER 10-5: RPINR8: PERIPHERAL PIN SELECT INPUT REGISTER 8 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-5 Unimplemented: Read as ‘0’ ...
Page 131
... AND dsPIC33FJ16MC101/102 REGISTER 10-6: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-5 Unimplemented: Read as ‘0’ ...
Page 132
... AND dsPIC33FJ16MC101/102 REGISTER 10-7: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 133
... AND dsPIC33FJ16MC101/102 REGISTER 10-8: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-5 Unimplemented: Read as ‘0’ ...
Page 134
... AND dsPIC33FJ16MC101/102 REGISTER 10-9: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 135
... AND dsPIC33FJ16MC101/102 REGISTER 10-11: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 136
... AND dsPIC33FJ16MC101/102 REGISTER 10-13: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 137
... AND dsPIC33FJ16MC101/102 REGISTER 10-15: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 138
... AND dsPIC33FJ16MC101/102 NOTES: DS70652C-page 138 Preliminary © 2011 Microchip Technology Inc. ...
Page 139
... AND dsPIC33FJ16MC101/102 11.0 TIMER1 Note 1: This data sheet summarizes the features of the dsPIC33FJ16GP101/102 and dsPIC33FJ16MC101/102 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 11. “Timers” (DS70205) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www ...
Page 140
... AND dsPIC33FJ16MC101/102 REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 (1) TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set (1) bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Read as ‘ ...
Page 141
... AND dsPIC33FJ16MC101/102 12.0 TIMER2/3 FEATURE Note 1: This data sheet summarizes the features of the dsPIC33FJ16GP101/102 and dsPIC33FJ16MC101/102 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 11. “Timers” (DS70205) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www ...
Page 142
... AND dsPIC33FJ16MC101/102 FIGURE 12-1: TIMER2/3 (32-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T3IF 0 (2) ADC Event Trigger Equal MSb Reset Read TMR2 Write TMR2 Data Bus<15:0> Note 1: The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register ...
Page 143
... AND dsPIC33FJ16MC101/102 FIGURE 12-2: TIMER2 (16-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T2IF 0 Reset Equal FIGURE 12-3: TIMER3 (16-BIT) BLOCK DIAGRAM Gate Sync Prescaler F CY TCKPS<1:0> Prescaler Sync (/n) TxCK TCKPS<1:0> To CTMU Filter © 2011 Microchip Technology Inc. Gate Sync TMR2 Comparator ...
Page 144
... AND dsPIC33FJ16MC101/102 REGISTER 12-1: T2CON CONTROL REGISTER R/W-0 U-0 R/W-0 TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TON: Timer2 On bit When T32 = Starts 32-bit Timer2/3 ...
Page 145
... AND dsPIC33FJ16MC101/102 REGISTER 12-2: T3CON CONTROL REGISTER R/W-0 U-0 R/W-0 (2) TON — TSIDL bit 15 U-0 R/W-0 R/W-0 (2) — TGATE TCKPS<1:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set (2) bit 15 TON: Timer3 On bit 1 = Starts 16-bit Timer3 0 = Stops 16-bit Timer3 bit 14 Unimplemented: Read as ‘ ...
Page 146
... AND dsPIC33FJ16MC101/102 NOTES: DS70652C-page 146 Preliminary © 2011 Microchip Technology Inc. ...
Page 147
... AND dsPIC33FJ16MC101/102 13.0 INPUT CAPTURE Note 1: This data sheet summarizes the features of the dsPIC33FJ16GP101/102 and dsPIC33FJ16MC101/102 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 12. “Input Cap- ture” (DS70198) in the “dsPIC33F/ PIC24H Family Reference Manual”, which is available from the Microchip web site (www ...
Page 148
... AND dsPIC33FJ16MC101/102 13.1 Input Capture Registers REGISTER 13-1: ICxCON: INPUT CAPTURE x CONTROL REGISTER U-0 U-0 R/W-0 — — ICSIDL bit 15 R/W-0 R/W-0 R/W-0 ICTMR ICI<1:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 149
... AND dsPIC33FJ16MC101/102 14.0 OUTPUT COMPARE Note 1: This data sheet summarizes the features of the dsPIC33FJ16GP101/102 and dsPIC33FJ16MC101/102 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 13. “Output Compare” (DS70209) of the “dsPIC33F/ PIC24H Family Reference Manual”, which is available from the Microchip web site (www ...
Page 150
... AND dsPIC33FJ16MC101/102 14.1 Output Compare Modes Configure the Output Compare modes by setting the appropriate Output Compare Mode (OCM<2:0>) bits in the Output Compare Control (OCxCON<2:0>) register. Table 14-1 lists the different bit settings for the Output Compare modes. Figure 14-2 illustrates the output compare operation for various modes ...
Page 151
... AND dsPIC33FJ16MC101/102 REGISTER 14-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER U-0 U-0 R/W-0 — — OCSIDL bit 15 U-0 U-0 U-0 — — — bit 7 Legend Cleared in Hardware R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 152
... AND dsPIC33FJ16MC101/102 NOTES: DS70652C-page 152 Preliminary © 2011 Microchip Technology Inc. ...
Page 153
... AND dsPIC33FJ16MC101/102 15.0 MOTOR CONTROL PWM MODULE Note 1: This data sheet summarizes the features of the dsPIC33FJ16GP101/102 and dsPIC33FJ16MC101/102 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 14. “Motor Con- trol PWM” (DS70187), in the “dsPIC33F/ PIC24H Family Reference Manual” ...
Page 154
... AND dsPIC33FJ16MC101/102 FIGURE 15-1: 6-CHANNEL PWM MODULE BLOCK DIAGRAM (PWM1) PWM1CON1 PWM1CON2 P1DTCON1 P1DTCON2 P1FLTACON P1FLTBCON P1OVDCON P1TMR Comparator P1TPER P1TPER Buffer P1TCON Comparator P1SECMP PWM Time Base Note 1: The details of PWM Generator 1 and 2 are not shown for clarity dsPIC33FJ16MC101 (20-pin) devices, the FLTA1 pin is supported, but requires an external pull-down resistor for correct functionality ...
Page 155
... AND dsPIC33FJ16MC101/102 15.2 PWM Faults The Motor Control PWM module incorporates up to two fault inputs, FLTA1 and FLTB1. These fault inputs are implemented with Class B safety features. These fea- tures ensure that the PWM outputs enter a safe state when either of the fault inputs is asserted. ...
Page 156
... AND dsPIC33FJ16MC101/102 EXAMPLE 15-1: ASSEMBLY CODE EXAMPLE FOR WRITE-PROTECTED REGISTER UNLOCK AND FAULT CLEARING SEQUENCE ; FLTA1 pin must be pulled high externally in order to clear and disable the fault ; Writing to P1FLTBCON register requires unlock sequence mov #0xabcd,w10 ; Load first unlock key to w10 register mov #0x4321,w11 ...
Page 157
... AND dsPIC33FJ16MC101/102 REGISTER 15-1: PxTCON: PWM TIME BASE CONTROL REGISTER R/W-0 U-0 R/W-0 PTEN — PTSIDL bit 15 R/W-0 R/W-0 R/W-0 PTOPS<3:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 PTEN: PWM Time Base Timer Enable bit ...
Page 158
... AND dsPIC33FJ16MC101/102 REGISTER 15-2: PxTMR: PWM TIMER COUNT VALUE REGISTER R-0 R/W-0 R/W-0 PTDIR bit 15 R/W-0 R/W-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 PTDIR: PWM Time Base Count Direction Status bit (read-only) ...
Page 159
... AND dsPIC33FJ16MC101/102 REGISTER 15-4: PxSECMP: SPECIAL EVENT COMPARE REGISTER R/W-0 R/W-0 R/W-0 (1) SEVTDIR bit 15 R/W-0 R/W-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 SEVTDIR: Special Event Trigger Time Base Direction bit Special Event Trigger will occur when the PWM time base is counting down ...
Page 160
... AND dsPIC33FJ16MC101/102 REGISTER 15-5: PWMxCON1: PWM CONTROL REGISTER 1 U-0 U-0 U-0 — — — bit 15 U-0 R/W-0 R/W-0 — PEN3H PEN2H bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 ...
Page 161
... AND dsPIC33FJ16MC101/102 REGISTER 15-6: PWMxCON2: PWM CONTROL REGISTER 2 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 SEVOPS< ...
Page 162
... AND dsPIC33FJ16MC101/102 REGISTER 15-7: PxDTCON1: DEAD-TIME CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 DTBPS<1:0> bit 15 R/W-0 R/W-0 R/W-0 DTAPS<1:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 DTBPS<1:0>: Dead-Time Unit B Prescale Select bits 11 = Clock period for Dead-Time Unit ...
Page 163
... AND dsPIC33FJ16MC101/102 REGISTER 15-8: PxDTCON2: DEAD-TIME CONTROL REGISTER 2 U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-0 — — DTS3A bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ bit 5 ...
Page 164
... AND dsPIC33FJ16MC101/102 REGISTER 15-9: PxFLTACON: FAULT A CONTROL REGISTER U-0 U-0 R/W-0 — — FAOV3H bit 15 R/W-0 U-0 U-0 FLTAM — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 FAOVxH< ...
Page 165
... AND dsPIC33FJ16MC101/102 REGISTER 15-10: PxFLTBCON: FAULT B CONTROL REGISTER U-0 U-0 R/W-0 — — FBOV3H bit 15 R/W-0 U-0 U-0 FLTBM — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 FBOVxH< ...
Page 166
... AND dsPIC33FJ16MC101/102 REGISTER 15-11: PxOVDCON: OVERRIDE CONTROL REGISTER U-0 U-0 R/W-1 — — POVD3H bit 15 U-0 U-0 R/W-0 — — POUT3H bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 POVDxH< ...
Page 167
... AND dsPIC33FJ16MC101/102 REGISTER 15-12: PxDC1: PWM DUTY CYCLE REGISTER 1 R/W-0 R/W-0 R/W-0 bit 15 R/W-0 R/W-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 PDC1<15:0>: PWM Duty Cycle 1 Value bits REGISTER 15-13: PxDC2: PWM DUTY CYCLE REGISTER 2 ...
Page 168
... AND dsPIC33FJ16MC101/102 REGISTER 15-15: PWMxKEY: PWM UNLOCK REGISTER R/W-0 R/W-0 R/W-0 bit 15 R/W-0 R/W-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 PWMKEY<15:0>: PWM Unlock bits If the PWMLOCK Configuration bit is asserted (PWMLOCK = 1), the PWMxCON1, PxFLTACON and PxFLTBCON registers are writable only after the proper sequence is written to the PWMxKEY register ...
Page 169
... AND dsPIC33FJ16MC101/102 16.0 SERIAL PERIPHERAL INTERFACE (SPI) Note 1: This data sheet summarizes the features of the dsPIC33FJ16GP101/102 and dsPIC33FJ16MC101/102 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 18. “Serial Peripheral Interface (SPI)” (DS70206) in the “dsPIC33F/PIC24H Reference Manual” ...
Page 170
... AND dsPIC33FJ16MC101/102 REGISTER 16-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 SPIEN — SPISIDL bit 15 U-0 R/C-0 U-0 — SPIROV — bit 7 Legend Clearable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 SPIEN: SPIx Enable bit ...
Page 171
... AND dsPIC33FJ16MC101/102 REGISTER 16-2: SPI CON1: SPIx CONTROL REGISTER 1 X U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 (2) SSEN CKP MSTEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 172
... AND dsPIC33FJ16MC101/102 REGISTER 16-2: SPI CON1: SPIx CONTROL REGISTER 1 (CONTINUED) X bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode) 111 = Secondary prescale 1:1 110 = Secondary prescale 2 000 = Secondary prescale 8:1 bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode Primary prescale 1:1 ...
Page 173
... AND dsPIC33FJ16MC101/102 REGISTER 16-3: SPIxCON2: SPIx CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 FRMEN SPIFSD FRMPOL bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 FRMEN: Framed SPIx Support bit 1 = Framed SPIx support enabled (SSx pin used as frame sync pulse input/output) ...
Page 174
... AND dsPIC33FJ16MC101/102 NOTES: DS70652C-page 174 Preliminary © 2011 Microchip Technology Inc. ...
Page 175
... AND dsPIC33FJ16MC101/102 17.0 INTER-INTEGRATED CIRCUIT™ C™) Note 1: This data sheet summarizes the features of the dsPIC33FJ16GP101/102 and dsPIC33FJ16MC101/102 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 19. “Inter-Inte- 2 grated Circuit™ (I C™)” (DS70195) in the “ ...
Page 176
... AND dsPIC33FJ16MC101/102 2 FIGURE 17-1: I C™ BLOCK DIAGRAM ( Shift SCLx Clock SDAx Shift Clock BRG Down Counter DS70652C-page 176 = 1) X I2CxRCV I2CxRSR LSb Address Match Match Detect I2CxADD Start and Stop Bit Detect Start and Stop Bit Generation Collision Detect ...
Page 177
... AND dsPIC33FJ16MC101/102 REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER R/W-0 U-0 R/W-0 I2CEN — I2CSIDL bit 15 R/W-0 R/W-0 R/W-0 GCEN STREN ACKDT bit 7 Legend Unimplemented bit, read as ‘0’ Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 I2CEN: I2Cx Enable bit 1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins 0 = Disables the I2Cx module ...
Page 178
... AND dsPIC33FJ16MC101/102 REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 5 ACKDT: Acknowledge Data bit (when operating as I Value that will be transmitted when the software initiates an Acknowledge sequence Send NACK during Acknowledge 0 = Send ACK during Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit ...
Page 179
... AND dsPIC33FJ16MC101/102 REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER R-0 HSC R-0 HSC U-0 ACKSTAT TRSTAT — bit 15 R/C-0 HS R/C-0 HS R-0 HSC IWCOL I2COV D_A bit 7 Legend Unimplemented bit, read as ‘0’ Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set ...
Page 180
... AND dsPIC33FJ16MC101/102 REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. bit 2 R_W: Read/Write Information bit (when operating Read – ...
Page 181
... AND dsPIC33FJ16MC101/102 REGISTER 17-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 AMSK7 AMSK6 AMSK5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-10 Unimplemented: Read as ‘0’ ...
Page 182
... AND dsPIC33FJ16MC101/102 NOTES: DS70652C-page 182 Preliminary © 2011 Microchip Technology Inc. ...
Page 183
... AND dsPIC33FJ16MC101/102 18.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) Note 1: This data sheet summarizes the features of the dsPIC33FJ16GP101/102 and dsPIC33FJ16MC101/102 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www ...
Page 184
... AND dsPIC33FJ16MC101/102 REGISTER 18-1: UxMODE: UART R/W-0 U-0 R/W-0 (1) UARTEN — USIDL bit 15 R/W-0 HC R/W-0 R/W-0 HC WAKE LPBACK ABAUD bit 7 Legend Hardware cleared R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 UARTEN: UARTx Enable bit 1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0> ...
Page 185
... AND dsPIC33FJ16MC101/102 REGISTER 18-1: UxMODE: UART bit 4 URXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is ‘0’ UxRX Idle state is ‘1’ bit 3 BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode BRG generates 16 clocks per bit period (16x baud clock, Standard mode) bit 2-1 PDSEL< ...
Page 186
... AND dsPIC33FJ16MC101/102 REGISTER 18-2: U STA: UART x R/W-0 R/W-0 R/W-0 UTXISEL1 UTXINV UTXISEL0 bit 15 R/W-0 R/W-0 R/W-0 URXISEL<1:0> ADDEN bit 7 Legend Hardware cleared R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15,13 UTXISEL<1:0>: Transmission Interrupt Mode Selection bits 11 = Reserved ...
Page 187
... AND dsPIC33FJ16MC101/102 REGISTER 18-2: U STA: UART x bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect 0 = Address Detect mode disabled bit 4 RIDLE: Receiver Idle bit (read-only Receiver is Idle ...
Page 188
... AND dsPIC33FJ16MC101/102 NOTES: DS70652C-page 188 Preliminary © 2011 Microchip Technology Inc. ...
Page 189
... AND dsPIC33FJ16MC101/102 19.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) Note 1: This data sheet summarizes the features of the dsPIC33FJ16GP101/102 and dsPIC33FJ16MC101/102 devices not intended compre- hensive reference source. To comple- ment the information in this data sheet, refer to Section 16. “Analog-to-Digital Converter (ADC)” (DS70183) in the “ ...
Page 190
... AND dsPIC33FJ16MC101/102 FIGURE 19-1: ADC1 BLOCK DIAGRAM FOR dsPIC33FJ16GP/MC101 AND DEVICES (1) CTMU TEMP (2) Open AN0 AN3 Channel Scan CH0SB<4:0> CH0SA<4:0> CH0 CSCNA AN1 AVss CH0NA CH0NB AN0 AN3 CH123SA CH123SB CH1 AVss CH123NA CH123NB AN1 CH123SA CH123SB CH2 AVss CH123NA CH123NB ...
Page 191
... AND dsPIC33FJ16MC101/102 FIGURE 19-2: ADC1 BLOCK DIAGRAM FOR dsPIC33FJ16GP/MC102 AND DEVICES (1) CTMU TEMP (2) Open AN0 AN5 Channel Scan CH0SB<4:0> CH0SA<4:0> CH0 CSCNA AN1 AVss CH0NA CH0NB AN0 AN3 CH123SA CH123SB CH1 AVss CH123NA CH123NB AN1 AN4 CH123SA CH123SB CH2 AVss ...
Page 192
... AND dsPIC33FJ16MC101/102 FIGURE 19-3: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM ADC Internal (1) RC Clock T CY OSC ( Note 1: See the ADC specifications in DS70652C-page 192 ADxCON3<5:0> 6 ADC Conversion Clock Multiplier 5,..., 64 Section 26.0 “Electrical Characteristics” Preliminary ADxCON3<15> for the exact RC clock value. ...
Page 193
... AND dsPIC33FJ16MC101/102 REGISTER 19-1: AD1CON1: ADC1 CONTROL REGISTER 1 R/W-0 U-0 R/W-0 ADON — ADSIDL bit 15 R/W-0 R/W-0 R/W-0 SSRC<2:0> bit 7 Legend Cleared by hardware R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ADON: ADC Operating Mode bit 1 = ADC module is operating ...
Page 194
... AND dsPIC33FJ16MC101/102 REGISTER 19-1: AD1CON1: ADC1 CONTROL REGISTER 1 (CONTINUED) bit 0 DONE: ADC Conversion Status bit 1 = ADC conversion cycle is completed 0 = ADC conversion not started or in progress Automatically set by hardware when ADC conversion is complete. Software can write ‘0’ to clear DONE status (software not allowed to write ‘1’). Clearing this bit will NOT affect any operation in progress ...
Page 195
... AND dsPIC33FJ16MC101/102 REGISTER 19-2: AD1CON2: ADC1 CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 VCFG<2:0> bit 15 R-0 U-0 R/W-0 BUFS — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 VCFG<2:0>: Converter Voltage Reference Configuration bits ADREF+ xxx ...
Page 196
... AND dsPIC33FJ16MC101/102 REGISTER 19-3: AD1CON3: ADC1 CONTROL REGISTER 3 R/W-0 U-0 U-0 ADRC — — bit 15 R/W-0 R/W-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ADRC: ADC Conversion Clock Source bit 1 = ADC internal RC clock ...
Page 197
... CH1, CH2, CH3 negative input is AVss bit 0 CH123SA: Channel Positive Input Select for Sample A bit dsPIC33FJ16GP101 and dsPIC33FJ16MC101 devices only CH1 positive input is AN3, CH2 and CH3 positive inputs are not connected 0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2 ...
Page 198
... Unimplemented: Read as ‘0’ bit 4-0 CH0SA<4:0>: Channel 0 Positive Input Select for Sample A bits dsPIC33FJ16GP101 and dsPIC33FJ16MC101 devices only: 01110 = No channels connected, all inputs floating (used for CTMU) 01101 = Channel 0 positive input is connected to CTMU temperature sensor 00011 = Channel 0 positive input is AN3 ...
Page 199
... AND dsPIC33FJ16MC101/102 ,2 REGISTER 19-6: AD1CSSL: ADC1 INPUT SCAN SELECT REGISTER LOW U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-0 — — CSS5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ ...
Page 200
... AND dsPIC33FJ16MC101/102 REGISTER 19-7: AD1PCFGL: ADC1 PORT CONFIGURATION REGISTER LOW U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-0 — — PCFG5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ ...