DSPIC33FJ16GP101-E/P Microchip Technology, DSPIC33FJ16GP101-E/P Datasheet - Page 173

• Manufacturer Part Number: DSPIC33FJ16GP101-E/P
• Description: 16-bit DSC Family, 16 MIPS, 16KB Flash, 1KB RAM 18 PDIP .300in TUBE
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16GP101-E/P

• Processor Series: dsPIC33F
• Core: dsPIC
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 16 KB
• Interface Type: SPI, I2C, UART, JTAG
• Number Of Programmable I/os: 35
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 125 C
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 16 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 13
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• A/d Bit Size: 10 bit
• A/d Channels Available: 13
• Lead Free Status / Rohs Status: Details

REGISTER 16-3:
© 2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-2
bit 1
bit 0
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
FRMEN
R/W-0
U-0
—
FRMEN: Framed SPIx Support bit
1 = Framed SPIx support enabled (SSx pin used as frame sync pulse input/output)
0 = Framed SPIx support disabled
SPIFSD: Frame Sync Pulse Direction Control bit
1 = Frame sync pulse input (slave)
0 = Frame sync pulse output (master)
FRMPOL: Frame Sync Pulse Polarity bit
1 = Frame sync pulse is active-high
0 = Frame sync pulse is active-low
Unimplemented: Read as ‘0’
FRMDLY: Frame Sync Pulse Edge Select bit
1 = Frame sync pulse coincides with first bit clock
0 = Frame sync pulse precedes first bit clock
Unimplemented: This bit must not be set to ‘1’ by the user application.
SPIFSD
R/W-0
U-0
—
SPIxCON2: SPIx CONTROL REGISTER 2
‘1’ = Bit is set
W = Writable bit
FRMPOL
R/W-0
U-0
—
U-0
U-0
Preliminary
—
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
U-0
—
—
U-0
U-0
—
—
x = Bit is unknown
FRMDLY
R/W-0
U-0
—
DS70652C-page 173
U-0
U-0
—
—
bit 8
bit 0