DSPIC33FJ16GP101-E/P Microchip Technology, DSPIC33FJ16GP101-E/P Datasheet - Page 155

• Manufacturer Part Number: DSPIC33FJ16GP101-E/P
• Description: 16-bit DSC Family, 16 MIPS, 16KB Flash, 1KB RAM 18 PDIP .300in TUBE
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16GP101-E/P

• Processor Series: dsPIC33F
• Core: dsPIC
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 16 KB
• Interface Type: SPI, I2C, UART, JTAG
• Number Of Programmable I/os: 35
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 125 C
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 16 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 13
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• A/d Bit Size: 10 bit
• A/d Channels Available: 13
• Lead Free Status / Rohs Status: Details

15.2
The Motor Control PWM module incorporates up to two
fault inputs, FLTA1 and FLTB1. These fault inputs are
implemented with Class B safety features. These fea-
tures ensure that the PWM outputs enter a safe state
when either of the fault inputs is asserted.
The FLTA and FLTB pins, when enabled and having
ownership of a pin, also enable a soft internal pull-down
resistor. The soft pull-down provides a safety feature by
automatically asserting the fault should a break occur
in the fault signal connection.
The implementation of internal pull-down resistors is
dependent on the device variant.
which devices and pins implement the internal pull-
down resistors.
TABLE 15-1:
On devices without internal pull-downs on the Fault pin,
it is recommended to connect an external pull-down
resistor for Class B safety features.
15.2.1
During any reset event, the PWM module maintains
ownership of both PWM Fault pins. At reset, both faults
are enabled in latched mode to guarantee the fail-safe
power-up of the application. The application software
must clear both the PWM faults before enabling the
Motor Control PWM module.
The Fault condition must be cleared by the external cir-
cuitry driving the fault input pin high and clearing the fault
interrupt flag. After the fault pin condition has been
cleared, the PWM module restores the PWM output
signals on the next PWM period or half-period boundary.
© 2011 Microchip Technology Inc.
dsPIC33FJ16MC101
dsPIC33FJ16MC102
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
Device
PWM Faults
PWM FAULTS AT RESET
INTERNAL PULL-DOWN
RESISTORS ON PWM FAULT
PINS
Fault Pin
FLTA1
FLTA1
FLTB1
Table 15-1
Implemented?
Internal Pull-
down
Yes
Yes
No
describes
Preliminary
Refer to Section 14. “Motor Control PWM”
(DS70187),
Reference Manual” for more information on the PWM
faults.
15.3
On dsPIC33FJ16MC101/102 devices, write protection
is implemented for the PWMxCON1, PxFLTACON and
PxFLTBCON registers. The write protection feature
prevents any inadvertent writes to these registers. The
write protection feature can be controlled by the
PWMLOCK configuration bit in the FOSCSEL configu-
ration register. The default state of the write protection
feature is enabled (PWMLOCK = 1). The write protec-
tion feature can be disabled by configuring PWMLOCK
(FOSCSEL<6>) = 0.
The user application can gain access to these locked
registers either by configuring the PWMLOCK (FOSC-
SEL<6>) = 0, or by performing the unlock sequence. To
perform the unlock sequence, the user application
must write two consecutive values of (0xABCD and
0x4321) to the PWMxKEY register to perform the
unlock operation. The write access to the PWMxCON1,
PxFLTACON or PxFLTBCON registers must be the
next SFR access following the unlock process. There
can be no other SFR accesses during the unlock pro-
cess and subsequent write access.
To write to all registers, the PWMxCON1, PxFLTACON
and PxFLTBCON registers require three unlock
operations.
The correct unlocking sequence is described in
Example 15-1
Note:
Write-protected Registers
The number of PWM faults mapped to the
device pins depend on the specific
variant. Regardless of the variant, both
faults will be enabled during any reset
event. The application must clear both
FLTA1 and FLTB1 before enabling the
Motor Control PWM module. Refer to the
specific device pin diagrams to see which
fault pins are mapped to the device pins.
in
and
Example
the
“dsPIC33F/PIC24H
15-2.
DS70652C-page 155
Family