DSPIC33FJ16GP101-E/P Microchip Technology, DSPIC33FJ16GP101-E/P Datasheet - Page 82

• Manufacturer Part Number: DSPIC33FJ16GP101-E/P
• Description: 16-bit DSC Family, 16 MIPS, 16KB Flash, 1KB RAM 18 PDIP .300in TUBE
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16GP101-E/P

• Processor Series: dsPIC33F
• Core: dsPIC
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 16 KB
• Interface Type: SPI, I2C, UART, JTAG
• Number Of Programmable I/os: 35
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 125 C
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 16 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 13
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• A/d Bit Size: 10 bit
• A/d Channels Available: 13
• Lead Free Status / Rohs Status: Details

dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
REGISTER 7-3:
DS70652C-page 82
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
SFTACERR
NSTDIS
R/W-0
R/W-0
NSTDIS: Interrupt Nesting Disable bit
1 = Interrupt nesting is disabled
0 = Interrupt nesting is enabled
OVAERR: Accumulator A Overflow Trap Flag bit
1 = Trap was caused by overflow of Accumulator A
0 = Trap was not caused by overflow of Accumulator A
OVBERR: Accumulator B Overflow Trap Flag bit
1 = Trap was caused by overflow of Accumulator B
0 = Trap was not caused by overflow of Accumulator B
COVAERR: Accumulator A Catastrophic Overflow Trap Flag bit
1 = Trap was caused by catastrophic overflow of Accumulator A
0 = Trap was not caused by catastrophic overflow of Accumulator A
COVBERR: Accumulator B Catastrophic Overflow Trap Flag bit
1 = Trap was caused by catastrophic overflow of Accumulator B
0 = Trap was not caused by catastrophic overflow of Accumulator B
OVATE: Accumulator A Overflow Trap Enable bit
1 = Trap overflow of Accumulator A
0 = Trap disabled
OVBTE: Accumulator B Overflow Trap Enable bit
1 = Trap overflow of Accumulator B
0 = Trap disabled
COVTE: Catastrophic Overflow Trap Enable bit
1 = Trap on catastrophic overflow of Accumulator A or B enabled
0 = Trap disabled
SFTACERR: Shift Accumulator Error Status bit
1 = Math error trap was caused by an invalid accumulator shift
0 = Math error trap was not caused by an invalid accumulator shift
DIV0ERR: Arithmetic Error Status bit
1 = Math error trap was caused by a divide by zero
0 = Math error trap was not caused by a divide by zero
Unimplemented: Read as ‘0’
MATHERR: Arithmetic Error Status bit
1 = Math error trap has occurred
0 = Math error trap has not occurred
ADDRERR: Address Error Trap Status bit
1 = Address error trap has occurred
0 = Address error trap has not occurred
DIV0ERR
OVAERR
R/W-0
R/W-0
INTCON1: INTERRUPT CONTROL REGISTER 1
W = Writable bit
‘1’ = Bit is set
OVBERR
R/W-0
U-0
—
COVAERR
MATHERR
R/W-0
R/W-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
COVBERR
ADDRERR
R/W-0
R/W-0
STKERR
OVATE
R/W-0
R/W-0
© 2011 Microchip Technology Inc.
x = Bit is unknown
OSCFAIL
OVBTE
R/W-0
R/W-0
COVTE
R/W-0
U-0
—
bit 8
bit 0