DSPIC33FJ64GP706AT-I/MR Microchip Technology, DSPIC33FJ64GP706AT-I/MR Datasheet - Page 330

• Manufacturer Part Number: DSPIC33FJ64GP706AT-I/MR
• Description: 16 Bit MCU/DSP 40MIPS 64KB FLASH 64 QFN 9x9x0.9mm T/R
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ64GP706AT-I/MR

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 18x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

dsPIC33FJXXXGPX06A/X08A/X10A
APPENDIX B:
Revision A (April 2009)
This is the initial release of this document.
TABLE B-1:
DS70593B-page 330
“High-Performance, 16-Bit Digital Signal
Controllers”
Section 10.0 “Power-Saving Features”
Section 11.0 “I/O Ports”
Section 18.0 “Universal Asynchronous
Receiver Transmitter (UART)”
Section 21.0 “10-Bit/12-Bit
Analog-to-Digital Converter (ADC)”
Section 22.0 “Special Features”
Section 25.0 “Electrical Characteristics”
Section 26.0 “High Temperature Electrical
Characteristics”
“Product Identification System”
Section Name
MAJOR SECTION UPDATES
REVISION HISTORY
Added information on high temperature operation (see “Operating
Range:”).
Updated the last paragraph to clarify the number of cycles that occur
prior to the start of instruction execution (see Section 10.2.2 “Idle
Mode”).
Changed the reference to digital-only pins to 5V tolerant pins in the
second paragraph of Section 11.2 “Open-Drain Configuration”.
Updated the two baud rate range features to: 10 Mbps to 38 bps at
40 MIPS.
Updated the ADCx block diagram (see Figure 21-1).
Updated the second paragraph and removed the fourth paragraph in
Section 22.1 “Configuration Bits”.
Updated the Device Configuration Register Map (see Table 22-1).
Added the FPWRT<2:0> bit field for the FWDT register to the
Configurative Bits Description table (see Table 22-1).
Updated the Absolute Maximum Ratings for high temperature and
added Note 4.
Updated Power-Down Current parameters DC60d, DC60a, DC60b,
and DC60d (see Table 25-7).
Added I2Cx Bus Data Timing Requirements (Master Mode)
parameter IM51 (see Table 25-32).
Updated the SPIx Module Slave Mode (CKE = 1) Timing
Characteristics (see Figure 25-12).
Updated the Internal LPRC Accuracy parameters (see Table 25-19).
Updated the ADC Module Specifications (12-bit Mode) parameters
AD23a and AD24a (see Table 25-38).
Updated the ADC Module Specifications (10-bit Mode) parameters
AD23b and AD24b (see Table 25-39).
Added new chapter with high temperature specifications.
Added the “H” definition for high temperature.
Preliminary
Revision B (October 2009)
The revision includes the following global update:
• Added Note 2 to the shaded table that appears at
This revision also includes minor typographical and
formatting changes throughout the data sheet text.
All other major changes are referenced by their
respective section in the following table.
the beginning of each chapter. This new note
provides information regarding the availability of
registers and their associated bits
Update Description
 2009 Microchip Technology Inc.