EP20K400CF672C7 Altera, EP20K400CF672C7 Datasheet - Page 2

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EP20K400CF672C7

Manufacturer Part Number
EP20K400CF672C7
Description
APEX 20KC
Manufacturer
Altera
Datasheet

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APEX 20KC Programmable Logic Device Data Sheet
...and More
Features
2
Note to
(1)
Internal supply voltage (V
MultiVolt I/O interface voltage levels (V
Table 2. APEX 20KC Supply Voltages
Low-power operation design
Flexible clock management circuitry with up to four phase-locked
loops (PLLs)
Powerful I/O features
APEX 20KC devices can be 5.0-V tolerant by using an external resistor.
Table
1.8-V supply voltage (see
Copper interconnect reduces power consumption
MultiVolt
ESBs offering programmable power-saving mode
Built-in low-skew clock tree
Up to eight global clock signals
ClockLock
ClockBoost
division
ClockShift
delay shifting
Compliant with peripheral component interconnect Special
Interest Group (PCI SIG) PCI Local Bus Specification,
Revision 2.2 for 3.3-V operation at 33 or 66 MHz and 32 or 64 bits
Support for high-speed external memories, including DDR
synchronous dynamic RAM (SDRAM) and ZBT static RAM
(SRAM)
16 input and 16 output LVDS channels at 840 megabits per
second (Mbps)
Direct connection from I/O pins to local interconnect providing
fast t
MultiVolt I/O support for 1.8-V, 2.5-V, and 3.3-V interfaces
Programmable clamp to V
Individual tri-state output enable control for each pin
Programmable output slew-rate control to reduce switching
noise
Support for advanced I/O standards, including low-voltage
differential signaling (LVDS), LVPECL, PCI-X, AGP, CTT,
SSTL-3 and SSTL-2, GTL+, and HSTL Class I
Supports hot-socketing operation
Pull-up on I/O pins before and during configuration
2:
CO
Feature
and t
TM
TM
TM
TM
I/O support for 1.8-V, 2.5-V, and 3.3-V interfaces
feature providing programmable clock phase and
SU
feature reducing clock delay and skew
feature providing clock multiplication and
CCINT
times for complex logic
)
Table
CCIO
CCIO
) 1.8 V, 2.5 V, 3.3 V, 5.0 V
2)
1.8 V
Voltage
Altera Corporation
(1)

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