EPF10K200SFC672-2 Altera, EPF10K200SFC672-2 Datasheet - Page 41

• Manufacturer Part Number: EPF10K200SFC672-2
• Description: FLEX 10KE
• Manufacturer: Altera

Altera Corporation
Notes to tables:
(1)
(2)
(3)
(4)
I/O
Configuration
t
t
t
f
f
f
t
t
t
t
CLK2
R
F
INDUTY
CLK1
CLKDEV
INCLKSTB
LOCK
JITTER
OUTDUTY
Table 13. ClockLock & ClockBoost Parameters for -2 Speed-Grade Devices
Symbol
To implement the ClockLock and ClockBoost circuitry with the MAX+PLUS II software, designers must specify the
input frequency. The Altera software tunes the PLL in the ClockLock and ClockBoost circuitry to this frequency.
The f
device operation. Simulation does not reflect this parameter.
Twenty-five thousand parts per million (PPM) equates to 2.5% of input clock period.
During device configuration, the ClockLock and ClockBoost circuitry is configured before the rest of the device. If
the incoming clock is supplied during configuration, the ClockLock and ClockBoost circuitry locks during
configuration because the t
The t
t
INCLKSTB
CLKDEV
JITTER
Input rise time
Input fall time
Input duty cycle
Input clock frequency (ClockBoost
clock multiplication factor equals 1)
Input clock frequency (ClockBoost
clock multiplication factor equals 2)
Input deviation from user
specification in the MAX+PLUS II
software
Input clock stability (measured
between adjacent clocks)
Time required for ClockLock or
ClockBoost to acquire lock
Jitter on ClockLock or ClockBoost-
generated clock
Duty cycle for ClockLock or
ClockBoost-generated clock
is lower than 50 ps.
specification is measured under long-term observation. The maximum value for t
parameter specifies how much the incoming clock can differ from the specified frequency during
(1)
Parameter
(4)
This section discusses the peripheral component interconnect (PCI)
pull-up clamping diode option, slew-rate control, open-drain output
option, and MultiVolt I/O interface for FLEX 10KE devices. The PCI
pull-up clamping diode, slew-rate control, and open-drain output options
are controlled pin-by-pin via Altera software logic options. The MultiVolt
I/O interface is controlled by connecting V
V
Project Device Options dialog box (Assign menu).
LOCK
CCINT
value is less than the time required for configuration.
(3)
. Its effect can be simulated in the Altera software via the Global
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
t
t
INCLKSTB
INCLKSTB
Condition
< 100
< 50
Min
40
25
16
40
CCIO
Typ
50
to a different voltage than
25,000
JITTER
200
Max
37.5
100
250
60
75
10
60
5
5
(4)
is 200 ps if
(2)
PPM
Unit
MHz
MHz
ns
ns
ps
µs
ps
ps
%
%
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