EPM7128BTC144-4 Altera, EPM7128BTC144-4 Datasheet - Page 12

• Manufacturer Part Number: EPM7128BTC144-4
• Description: MAX 7000/S/AE/B
• Manufacturer: Altera

MAX 7000B Programmable Logic Device Data Sheet
12
Figure 5. MAX 7000B PIA Routing
While the routing delays of channel-based routing schemes in masked or
field-programmable gate arrays (FPGAs) are cumulative, variable, and
path-dependent, the MAX 7000B PIA has a predictable delay. The PIA
makes a design’s timing performance easy to predict.
I/O Control Blocks
The I/O control block allows each I/O pin to be individually configured
for input, output, or bidirectional operation. All I/O pins have a tri-state
buffer that is individually controlled by one of the global output enable
signals or directly connected to ground or V
control block for MAX 7000B devices. The I/O control block has
six or ten global output enable signals that are driven by the true or
complement of two output enable signals, a subset of the I/O pins, or a
subset of the I/O macrocells.
PIA Signals
CC
.
Figure 6
Altera Corporation
shows the I/O
To LAB