EPM7160EQC160-12 Altera, EPM7160EQC160-12 Datasheet - Page 34

• Manufacturer Part Number: EPM7160EQC160-12
• Description: MAX 7000/S/AE/B
• Manufacturer: Altera

MAX 7000 Programmable Logic Device Family Data Sheet
34
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
f
f
PD1
PD2
SU
H
FSU
FH
CO1
CH
CL
ASU
AH
ACO1
ACH
ACL
CPPW
ODH
CNT
CNT
ACNT
ACNT
MAX
Table 22. MAX 7000 & MAX 7000E External Timing Parameters
Input to non-registered output
I/O input to non-registered
output
Global clock setup time
Global clock hold time
Global clock setup time of fast
input
Global clock hold time of fast
input
Global clock to output delay
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output delay
Array clock high time
Array clock low time
Minimum pulse width for clear
and preset
Output data hold time after
clock
Minimum global clock period
Maximum internal global clock
frequency
Minimum array clock period
Maximum internal array clock
frequency
Maximum clock frequency
Parameter
C1 = 35 pF
C1 = 35 pF
(2)
(2)
C1 = 35 pF
C1 = 35 pF
(3)
C1 = 35 pF
(5)
(5)
(6)
Conditions
(4)
Min
11.0
76.9
76.9
100
0.0
3.0
0.0
5.0
5.0
4.0
4.0
6.0
6.0
6.0
1.0
-15
Max
15.0
15.0
15.0
13.0
13.0
8.0
Note (1)
Speed Grade
Min
11.0
76.9
76.9
83.3
0.0
6.0
6.0
4.0
4.0
6.5
6.5
6.5
1.0
–
–
-15T
Max
15.0
15.0
15.0
13.0
13.0
8.0
Min
12.0
62.5
62.5
83.3
0.0
5.0
0.0
6.0
6.0
5.0
5.0
8.0
8.0
8.0
1.0
Altera Corporation
-20
Max
20.0
20.0
12.0
20.0
16.0
16.0
Unit
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns