EPM9320LC84-20 Altera, EPM9320LC84-20 Datasheet

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EPM9320LC84-20

Manufacturer Part Number
EPM9320LC84-20
Description
MAX 9000
Manufacturer
Altera
Datasheet

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Features...
Altera Corporation
DS-M9000-6.5
June 2003, ver. 6.5
Usable gates
Flipflops
Macrocells
Logic array blocks (LABs)
Maximum user I/O pins
t
t
t
f
Table 1. MAX 9000 Device Features
PD1
FSU
FCO
CNT
(ns)
(ns)
(MHz)
(ns)
Feature
EPM9320
EPM9320A
High-performance CMOS EEPROM-based programmable logic
devices (PLDs) built on third-generation Multiple Array MatriX
(MAX
5.0-V in-system programmability (ISP) through built-in IEEE Std.
1149.1 Joint Test Action Group (JTAG) interface
Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE
Std. 1149.1-1990
High-density erasable programmable logic device (EPLD) family
ranging from 6,000 to 12,000 usable gates (see
10-ns pin-to-pin logic delays with counter frequencies of up to
144 MHz
Fully compliant with the peripheral component interconnect Special
Interest Group’s (PCI SIG) PCI Local Bus Specification, Revision 2.2
Dual-output macrocell for independent use of combinatorial and
registered logic
FastTrack
Input/output registers with clear and clock enable on all I/O pins
Programmable output slew-rate control to reduce switching noise
MultiVolt
3.3-V and 5.0-V devices
Configurable expander product-term distribution allowing up to 32
product terms per macrocell
Programmable power-saving mode for more than 50% power
reduction in each macrocell
6,000
484
320
168
144
3.0
4.5
20
10
®
) architecture
®
®
Interconnect for fast, predictable interconnect delays
I/O interface operation, allowing devices to interface with
EPM9400
MAX 9000A
8,000
Includes
580
400
159
118
25
15
5
7
EPM9480
10,000
Programmable Logic
676
480
175
144
3.0
4.8
30
10
Table
Device Family
MAX 9000
1)
EPM9560
EPM9560A
12,000
Data Sheet
772
560
216
144
3.0
4.8
35
10
1

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