EVAL-AD5263EBZ Analog Devices Inc, EVAL-AD5263EBZ Datasheet - Page 21

• Manufacturer Part Number: EVAL-AD5263EBZ
• Description: EVALUATION BOARD I.C.
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5263EBZ

• Main Purpose: Digital Potentiometer
• Embedded: No
• Utilized Ic / Part: AD5263
• Primary Attributes: 4 Channel, 256 Position
• Secondary Attributes: I²C & SPI Interfaces
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

However, the digital inputs must also be level shifted to allow
proper operation because the ground is referenced to the
negative potential. As a result, Figure 51 shows one implement-
tation with a couple of transistors and a few resistors. When V
is high, Q1 is turned on and its emitter is clamped at one
threshold above ground. This threshold appears at the base of
Q2, which causes Q2 to turn off. In this state, V
−5 V. When V
pulled low, which in turn causes Q2 to turn on. In this state,
V
needed for successful communication with the device.
ESD PROTECTION
All digital inputs are protected with a series input resistor and
parallel Zener ESD structures shown in Figure 52 and Figure 53.
This protection applies to digital input pins SDI/SDA, CLK/SCL,
CS /AD0, RES /AD1, and SHDN .
TERMINAL VOLTAGE OPERATING RANGE
The AD5263 positive V
defines the boundary conditions for proper 3-terminal digital
potentiometer operation. Supply signals present on the A, B,
and W terminals that exceed V
internal forward-biased diodes shown in Figure 54.
+5V
OUT
0V
approaches 0 V. Beware that proper time shifting is also
Figure 51. Level Shift for Bipolar Potential Operation
Figure 53. ESD Protection of Resistor Terminals
V
IN
IN
Figure 52. ESD Protection of Digital Pins
is low, Q1 is turned off and the base of Q2 is
1kΩ
R3
A,B,W
DD
–5V
340Ω
V
and negative V
Q1
2N3906
SS
R1
10kΩ
V
SS
DD
LOGIC
or V
2N3906
Q2
SS
are clamped by the
–5V
SS
R2
10kΩ
power supply
OUT
–5V
0V
V
OUT
approaches
Rev. B | Page 21 of 28
IN
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at the A, B, and W terminals (see Figure 54), it is important to
power V
W terminals; otherwise, the diodes are forward biased such that
V
of the circuit. The ideal power-up sequence is in the following
order: GND, V
order of powering V
important as long as they are powered after V
V
The AD5263 is capable of operating at high voltages beyond the
internal logic levels, which are limited to operation at 5 V. As a
result, V
source to ensure proper digital signal levels. Logic levels must
be limited to V
always be less than or equal to V
LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to employ compact, minimum-lead length
layout design. The leads to the input should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Similarly, it is also a good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to
the device should be bypassed with 0.01 μF to 0.1 μF ceramic
disc or chip capacitors. Low ESR 1 μF to 10 μF tantalum or
electrolytic capacitors should also be applied at the supplies to
minimize any transient disturbance and low frequency ripple
(see Figure 55). Notice the digital ground should also be joined
remotely to the analog ground at one point to minimize the
ground bounce.
DD
LOGIC
and V
POWER SUPPLY
Figure 54. Maximum Terminal Voltages Set by V
DD
L
always needs to be tied to a separate 2.7 V to 5.5 V
SS
and V
V
V
are powered unintentionally and may affect the rest
DD
SS
10µF
10µF
C3
C4
DD
L
, regardless of V
, V
SS
Figure 55. Power Supply Bypassing
+
+
before applying any voltage to the A, B, and
SS
A
0.1µF
0.1µF
, V
, V
C1
C2
L
B
, digital inputs, and V
, V
W
, and digital inputs is not
DD
DD
. In addition, V
.
V
V
DD
SS
AD5263
GND
DD
A/B/W
DD
and V
V
A
W
B
V
L
DD
SS
and V
should
. The relative
AD5263
SS
SS
.