EVAL-ADUC7060QSPZ Analog Devices Inc, EVAL-ADUC7060QSPZ Datasheet
EVAL-ADUC7060QSPZ
Specifications of EVAL-ADUC7060QSPZ
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EVAL-ADUC7060QSPZ Summary of contents
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FEATURES Analog input/output Dual (24-bit) ADCs Single-ended and differential inputs Programmable ADC output rate ( kHz) Programmable digital filters Built-in system calibration Low power operation mode Primary (24-bit) ADC channel input channels PGA (1 ...
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ADuC7060 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Functional Block Diagram .............................................................. 3 Specifications ..................................................................................... 4 Electrical Specifications ............................................................... 4 Timing Specifications .................................................................. 9 Absolute Maximum Ratings .......................................................... 13 ESD ...
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FUNCTIONAL BLOCK DIAGRAM ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 IEXC0 IEXC1 DAC0 BUF VREF+ VREF– GND_SW PRECISION ANALOG PERIPHERALS POR 24-BIT MUX PGA Σ-Δ ADC ARM7TDMI MCU 10MHz 24-BIT MUX BUF Σ-Δ ADC 4× TIMERS WDT ...
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ADuC7060 SPECIFICATIONS ELECTRICAL SPECIFICATIONS V = 2.5 V ± 5%, VREF+ = 1.2 V, VREF− = GND internal reference on-chip precision oscillator, all specifications T in Table 36 (ADC auxiliary channel) and Table 34 (primary ADC). Table ...
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Parameter Test Conditions/Comments Full-Scale Error Low power mode 9 Gain Drift vs. Temperature Power Supply Rejection Chop on, ADC = 1 V Chop off, ADC = 1 V ADC SPECIFICATIONS: ANALOG Internal V INPUT Main Channel Absolute ...
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ADuC7060 Parameter Test Conditions/Comments VOLTAGE REFERENCE ADC Precision Reference Internal V REF Initial Accuracy Measured at T Reference Temperature Coefficient Power Supply Rejection External Reference Input 12 Range 1 V Divide-by-2 Initial Error REF DAC CHANNEL SPECIFICATIONS ...
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Parameter Test Conditions/Comments RESET Timeout from POR Maximum supply ramp between 1 2.25 V; after POR trip, DVDD must reach 2.25 V within this time limit EXCITATION CURRENT SOURCES Output Current Available from each current source Initial Tolerance ...
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ADuC7060 Parameter Test Conditions/Comments PLL Off Wakeup from Interrupt Internal PLL Lock Time POWER REQUIREMENTS Power Supply Voltages DVDD (±5%) AVDD (±5%) Power Consumption 18 I (MCU Normal Mode) MCU clock rate = 10.24 MHz, DD ADC ...
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TIMING SPECIFICATIONS Timing 2 Table Timing in Standard Mode (100 kHz) Parameter Description t SCLOCK low pulse width L t SCLOCK high pulse width H t Start condition hold time SHD t Data setup ...
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ADuC7060 SPI Timing Table 3. SPI Master Mode Timing (Phase Mode = 1) Parameter Description t SCLOCK low pulse width SL t SCLOCK high pulse width SH t Data output valid after SCLOCK edge DAV t Data input setup time ...
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SCLOCK (POLARITY = 0) SCLOCK (POLARITY = 1) t DOSU MOSI MISO t DSU Table 5. SPI Slave Mode Timing (Phase Mode = 1) Parameter Description SCLOCK edge CS t SCLOCK low pulse width SL t ...
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ADuC7060 Table 6. SPI Slave Mode Timing (Phase Mode = 0) Parameter Description SCLOCK edge CS t SCLOCK low pulse width SL t SCLOCK high pulse width SH t Data output valid after SCLOCK edge DAV ...
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ABSOLUTE MAXIMUM RATINGS T = −40°C to +125°C, unless otherwise noted. A Table 7. Parameter AGND to DGND to AVDD to DVDD Digital I/O Voltage to DGND VREF± to AGND ADC Inputs to AGND ESD (Human Body Model) Rating All ...
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ADuC7060 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS P1.0/IRQ1/SIN/T0 ADC5/EXT_REF2IN− NOTES CONNECT. 2. THE LFCSP_VQ ONLY HAS AN EXPOSED PADDLE THAT MUST BE LEFT UNCONNECTED. THIS DOES NOT APPLY TO THE LQFP. Table 8. Pin Function Descriptions Pin ...
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Pin No. Mnemonic Type 13 ADC4/EXT_REF2IN ADC3 I 15 ADC2 I 16 IEXC1 O 17 IEXC0 O 18 GND_SW I 19 ADC1 I 20 ADC0 I 21 VREF VREF− AGND S 24 AVDD S ...
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ADuC7060 Pin No. Mnemonic Type 46 TDO O 47 TDI I 48 TCK input output supply. 1 Description JTAG Data Out. Output pin used for debug and download only. JTAG Data In. ...
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TERMINOLOGY Conversion Rate The conversion rate specifies the rate at which an output result is available from the ADC, once the ADC has settled. The sigma-delta (Σ-Δ) conversion techniques used on this part mean that while the ADC front-end signal ...
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ADuC7060 OVERVIEW OF THE ARM7TDMI CORE The ARM7 core is a 32-bit, reduced instruction set computer (RISC), developed by ARM® Ltd. The ARM7TDMI is a von Neumann-based architecture, meaning that it uses a single 32-bit bus for instruction and data. ...
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The stack pointer contains the current location of the stack. Generally ARM7TDMI, the stack starts at the top of the available RAM area and descends using the area as required. A separate stack is defined for each of ...
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ADuC7060 SRAM The ADuC7060 features SRAM, organized as 1024 × 32 bits, that is, 1024 words located at 0x40000. The RAM space can be used as data memory as well as volatile program space. ARM code can ...
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Table 13. FEEMOD MMR Bit Designations Bit Description 15:9 Reserved. 8 Reserved. Always set this bit to 0. 7:5 Reserved. Always set these bits to 0 except when writing keys. 4 Flash/EE interrupt enable. Set by user to enable the ...
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ADuC7060 FEEDAT Register FEEDAT is a 16-bit data register. This register holds the data value for flash read and write commands. Name: FEEDAT Address: 0xFFFF0E0C Default value: 0xXXXX Access: Read and write FEEADR Register FEEADR is a 16-bit address register ...
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MEMORY MAPPED REGISTERS The memory mapped register (MMR) space is mapped into the upper two pages of the memory array and accessed by indirect addressing through the ARM7 banked registers. The MMR space provides an interface between the CPU and ...
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ADuC7060 COMPLETE MMR LISTING In the following MMR tables, addresses are listed in hexadecimal code. Access types include R for read, W for write, and R/W for read and write. Table 16. IRQ Address Base = 0xFFFF0000 Address Name Byte ...
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Table 18. Timer Address Base = 0xFFFF0300 Access Address Name Byte Type 0x0320 T0LD 4 R/W 0x0324 T0VAL 4 R 0x0328 T0CON 4 R/W 0x032C T0CLRI 1 R/W 0x0330 T0CAP 4 R 0x0340 T1LD 4 R/W 0x0344 T1VAL 4 R ...
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ADuC7060 Table 20. ADC Address Base = 0xFFFF0500 Access Address Name Byte Type 0x0500 ADCSTA 2 R 0x0504 ADCMSKI 2 R/W 0x0508 ADCMDE 1 R/W 0x050C ADC0CON 2 R/W 0x0510 ADC1CON 2 R/W 0x0514 ADCFLT 2 R/W 0x0518 ADCCFG 1 ...
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Table 23 Base Address = 0xFFFF0900 Access Address Name Byte Type 0x0900 I2CMCON 2 R/W 0x0904 I2CMSTA 2 R 0x0908 I2CMRX 1 R 0x090C I2CMTX 1 W 0x0910 I2CMCNT0 2 R/W 0x0914 I2CMCNT1 1 R 0x0918 I2CADR0 ...
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ADuC7060 Table 26. Flash/EE Base Address = 0xFFFF0E00 Access Address Name Byte Type 0x0E00 FEESTA 2 R 0x0E04 FEEMOD 2 RW 0x0E08 FEECON 1 RW 0x0E0C FEEDAT 2 RW 0x0E10 FEEADR 2 RW 0x0E18 FEESIGN 3 R 0x0E1C FEEPRO 4 ...
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RESET There are four kinds of reset: external reset, power-on-reset, watchdog reset, and software reset. The RSTSTA register indicates the source of the last reset and can be written by user code to initiate a software reset event. The bits ...
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ADuC7060 OSCILLATOR, PLL, AND POWER CONTROL Clocking System The ADuC7060 integrates a 32.768 kHz ±3% oscillator, a clock divider, and a PLL. The PLL locks onto a multiple of the inter- nal oscillator or an external 32.768 kHz crystal to ...
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Power and Clock Control Registers Name: POWKEY1 Address: 0xFFFF0404 Default value: 0xXXXX Access: Write Function: When writing to POWCON0, the value of 0x01 must be written to this register in the instruction immediately before writing to POWCON0. Table 30. POWCON0 ...
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ADuC7060 Table 32. Typical Current Consumption at 25° POWCON0[6:3] Mode 2 1111 Active 3 1110 Pause 3 1100 Nap 3 1000 Sleep 0000 Stop 3 1 All values listed in Table 32 have been taken with both ADCs ...
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ADC CIRCUIT INFORMATION INTERNAL REFERENCE IEXC0 IEXC1 ADC0 ADC1 CHOP MUX ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 GND_SW 50Ω AGND TEMPERATURE The ADuC7060 incorporates two independent multichannel Σ-Δ ADCs. The primary ADC is a 24-bit, 5-channel ADC. The ...
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ADuC7060 Table 34. Primary ADC—Typical Output RMS Noise in Normal Mode (μV) ADC Data Register Update ±1.2 mV ±600 mV Status Rate (PGA = 1) (PGA = 2) Chop 0.62 μV 0.648 μV Chop Off 50 Hz ...
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Table 37. Example Scenarios for Using Diagnostic Current Sources Diagnostic Test Register Setting Description ADC0DIAG[1: Convert ADC0/ADC1 as normal with diagnostic currents disabled. ADC0DIAG[1: Enable a 50 μA diagnostic current source on ADC0 by setting ADC0DIAG[1:0] ...
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ADuC7060 ADC Comparator and Accumulator Every primary ADC result can be compared to a preset threshold level (ADC0TH) as configured via ADCCFG[4:3]. An MCU interrupt is generated if the absolute (sign independent) value of the ADC result is greater than ...
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Table 38. ADCSTA MMR Bit Designations Bit Name Description 15 ADCCALSTA ADC calibration status. This bit is set automatically in hardware to indicate that an ADC calibration cycle has been completed. This bit is cleared after ADCMDE is written to. ...
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ADuC7060 ADC Interrupt Mask Register Name: ADCMSKI Address: 0xFFFF0504 Default value: 0x0000 Access: Read and write Function: This register allows the ADC interrupt sources to be enabled individually. The bit positions in this register are the same as the lower ...
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Bit Name Description ADCLPMCFG[1:0] ADC power mode configuration ADC normal mode. If enabled, the ADC operates with normal current consumption yielding optimum electrical performance ADC low power mode ...
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ADuC7060 Table 41. ADC0CON MMR Bit Designations Bit Name Description 15 ADC0EN Primary channel ADC enable. This bit is set user code to enable the primary ADC. Clearing this bit to 0 powers down the primary ADC ...
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Auxiliary ADC Control Register Name: ADC1CON Address: 0xFFFF0510 Default value: 0x0000 Access: Read and write Function: The auxiliary ADC control MMR is a 16-bit register. Table 42. ADC1CON MMR Bit Designations Bit Name Description 15 ADC1EN Auxiliary channel ADC enable. ...
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ADuC7060 Bit Name Description 6:4 ADC1REF[2:0] Auxiliary channel ADC reference select. [000] = internal reference selected. In ADC low power mode, the voltage reference selection is controlled by ADCMODE[5]. [001] = external reference inputs (VREF+, VREF−) selected. Set the HIGHEXTREF1 ...
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Bit Name Description 7 NOTCH2 Sinc3 modify. Set by user to modify the standard sinc3 frequency response to increase the filter stop band rejection by approximately 5 dB. This is achieved by inserting a second notch (NOTCH2 ...
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ADuC7060 ADC Configuration Register Name: ADCCFG Address: 0xFFFF0518 Default value: 0x00 Access: Read and write Function: The 8-bit ADC configuration MMR controls extended functionality related to the on-chip ADCs. Table 46. ADCCFG MMR Bit Designations Bit Name Description 7 GNDSW_EN ...
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Primary Channel ADC Data Register Name: ADC0DAT Address: 0xFFFF051C Default value: 0x00000000 Access: Read only Function: This ADC data MMR holds the 24-/16-bit conversion result from the primary ADC. The ADC does not update this MMR if the ADC0 conversion ...
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ADuC7060 Table 50. ADC1OF MMR Bit Designations Bits Description ADC1 16-bit calibration offset value. Primary Channel ADC Gain Calibration Register Name: ADC0GN Address: 0xFFFF052C Default value: Part specific, factory programmed Access: Read and write Function: This gain ...
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Primary Channel ADC Threshold Register Name: ADC0TH Address: 0xFFFF053C Default value: 0x0000 Access: Read and write Function: This 16-bit MMR sets the threshold against which the absolute value of the primary ADC conversion result is compared. In unipolar mode, ADC0TH[15:0] ...
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ADuC7060 Table 58. ADC0ACC MMR Bit Designations Bits Description ADC0 32-bit threshold exceeded counter register. Table 59. ADC0ATH MMR Bit Designations Bits Description ADC0 32-bit comparator threshold register of the accumulator. ADC0 MAIN ADC ...
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Excitation Current Sources Control Register Name: IEXCON Address: 0xFFFF0570 Default value: 0x00 Access: Read and write Function: This 8-bit MMR controls the two excitation current sources, IEXC0 and IEXC1. Table 60. IEXCON MMR Bit Designations Bits Name Description 7 IEXC1_EN ...
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ADuC7060 ADuC7060 +2.5V AVDD/DVDD VREF+ ADC0 ADC1 VREF– AGND/DGND Figure 17. Bridge Interface Circuit ADuC7060 ADC0 AVDD/DVDD ADC1 AD592 ADC4 ADR280 VREF+ VREF– AGND/DGND Figure 18. Example of a Thermocouple Interface Circuit SPI RTD UART GPIO +2.5V ...
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DAC PERIPHERALS DAC The ADuC7060 incorporates a 12-bit voltage output DAC on- chip. The DAC has a rail-to-rail voltage output buffer capable of driving 5 kΩ/100 pF. The DAC has four selectable ranges. • (internal band ...
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ADuC7060 DAC0DAT Register Name: DAC0DAT Address: 0xFFFF0604 Default value: 0x00000000 Access: Read and write Function: This 32-bit MMR contains the DAC output value. Table 62. DAC0DAT MMR Bit Designations Bit Description 31:28 Reserved. 27:16 12-bit data for DAC0. 15:12 Extra ...
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NONVOLATILE FLASH/EE MEMORY The ADuC7060 incorporates Flash/EE memory technology on-chip to provide the user with nonvolatile, in-circuit reprogram- mable memory space. Like EEPROM, flash memory can be programmed in-system at a byte level, although it must first be erased. The ...
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ADuC7060 PROCESSOR REFERENCE PERIPHERALS INTERRUPT SYSTEM There are 15 interrupt sources on the ADuC7060 that are con- trolled by the interrupt controller. All interrupts are generated from the on-chip peripherals, except for the software interrupt (SWI), which is programmable by ...
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IRQCLR Register Name: IRQCLR Address: 0xFFFF000C Default value: 0x00000000 Access: Write only IRQSTA IRQSTA is a read-only register that provides the current enabled IRQ source status (effectively a logic AND of the IRQSIG and IRQEN bits). When set to 1, ...
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ADuC7060 FIQSTA Register Name: FIQSTA Address: 0xFFFF0100 Default value: 0x00000000 Access: Read only PROGRAMMED INTERRUPTS Because the programmed interrupts are not maskable, they are controlled by another register (SWICFG) that writes into both IRQSTA and IRQSIG registers and/or the FIQSTA ...
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Table 66. IRQVEC MMR Bit Designations Initial Bit Type Value Description 31:23 Read 0 Always read as 0. only 22:7 Read 0 IRQBASE register value. only 6:2 Read 0 Highest priority IRQ source. This only is a value between 0 ...
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ADuC7060 IRQCONN The IRQCONN register is the IRQ and FIQ control register. It contains two active bits. The first to enable nesting and prioritization of IRQ interrupts the other to enable nesting and prioritization of FIQ interrupts. If these bits ...
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FIQSTAN If IRQCONN.1 is asserted and FIQVEC is read, then one of these bits asserts. The bit that asserts depends on the priority of the FIQ. If the FIQ is of Priority 0 then Bit 0 asserts, Priority 1 then ...
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ADuC7060 IRQCLRE Register Name: IRQCLRE Address: 0xFFFF0038 Default value: 0x00000000 Access: Read and write Table 75. IRQCLRE MMR Bit Designations Bit Name Description 31:20 Reserved These bits are reserved and should not be written to. 19 IRQ3CLRI A 1 must ...
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TIMERS The ADuC7060 features four general-purpose timer/counters. • Timer0 • Timer1 or wake-up timer • Timer2 or watchdog timer • Timer3 The four timers in their normal mode of operation can be either free running or periodic. In free running ...
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ADuC7060 TIMER0 Timer0 is a 32-bit general-purpose timer, count down or count up, with a programmable prescaler. The prescaler source can be the low power 32.768 kHz oscillator, the core clock, or from one of two external GPIOs. This source ...
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Timer0 Capture Register Name: T0CAP Address: 0xFFFF0330 Default value: 0x00000000 Access: Read only Function: This 32-bit register holds the 32-bit value captured by an enabled IRQ event. Timer0 Control Register Name: T0CON Address: 0xFFFF0328 Default value: 0x01000000 Access: Read and ...
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ADuC7060 Bit Name Description 6 T0MOD Timer0 mode. Set by user to operate in periodic mode. Cleared by user to operate in free running mode (default T0FORMAT Format binary (default reserved ...
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OSCILLATOR CORE CLOCK FREQUENCY/CD CLOCK EXTERNAL 32.768kHz WATCH CRYSTAL Timer1 Control Register Name: T1CON Address: 0xFFFF0348 Default value: 0x0000 Access: Read and write Function: This 16-bit MMR configures the mode of operation of Timer1. Table 78. T1CON MMR Bit ...
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ADuC7060 TIMER2 OR WATCHDOG TIMER Timer2 has two modes of operation, normal mode and watchdog mode. The watchdog timer is used to recover from an illegal software state. When enabled, it requires periodic servicing to prevent it from forcing a ...
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Timer2 Control Register Name: T2CON Address: 0xFFFF0368 Default value: 0x0000 Access: Read and write Function: The 16-bit MMR configures the mode of operation of Timer2, as described in detail in Table 79. Table 79. T2CON MMR Bit Designations Bit Name ...
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ADuC7060 TIMER3 Timer3 is a general-purpose, 16-bit, count up/count down timer with a programmable prescaler. Timer3 can be clocked from the core clock or the low power 32.768 kHz oscillator with a prescaler of 1, 16, 256, or 32,768. Timer3 ...
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Table 80. T3CON MMR Bit Designations Bit Name Description 31:18 Reserved. 17 T3CAPEN Event enable bit. Set by user to enable time capture of an event. Cleared by user to disable time capture of an event. 16:12 T3CAPSEL Event select ...
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ADuC7060 PULSE-WIDTH MODULATOR PULSE-WIDTH MODULATOR GENERAL OVERVIEW The ADuC7060 integrates a 6-channel pulse-width modulator (PWM) interface. The PWM outputs can be configured to drive an H-bridge or can be used as standard PWM outputs. On power-up, the PWM outputs default ...
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Table 82. PWMCON MMR Bit Designations Bit Name Description 14 Sync Enables PWM synchronization. Set user so that all PWM counters are reset on the next clock edge after the detection of a high-to-low transition on the ...
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ADuC7060 On power-up, PWMCON defaults to 0x0012 (HOFF = 1 and HMODE = 1). All GPIO pins associated with the PWM are configured in PWM mode by default (see Table 84). Clear the PWM trip interrupt by writing any value ...
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PWM0COM0 Compare Register Name: PWM0COM0 Address: 0xFFFF0F84 Default value: 0x0000 Access: Read and write Function: PWM0 output pin goes high when the PWM timer reaches the count value stored in this register. PWM0COM1 Compare Register Name: PWM0COM1 Address: 0xFFF0F88 Default ...
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ADuC7060 PWM2COM0 Compare Register Name: PWM2COM0 Address: 0xFFF0FA4 Default value: 0x0000 Access: Read and write Function: PWM4 output pin goes high when the PWM timer reaches the count value stored in this register. PWM2COM1 Compare Register Name: PWM2COM1 Address: 0xFFF0FA8 ...
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UART SERIAL INTERFACE The ADuC7060 features a 16,450-compatible UART. The UART is a full-duplex, universal, asynchronous receiver/transmitter. A UART performs serial-to-parallel conversion on data characters received from a peripheral device and parallel-to-serial conversion on data characters received from the ARM7TDMI. ...
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ADuC7060 UART Transmit Register Write to this 8-bit register (COMTX) to transmit data using the UART. COMTX Register Name: COMTX Address: 0xFFFF0700 Access: Write only UART Receive Register This 8-bit register (COMRX) is read to receive data transmitted using the ...
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Table 87. COMCON0 MMR Bit Designations Bit Name 7 DLAB 6 BRK EPS 3 PEN 2 Stop 1:0 WLS Description Divisor latch access. Set by user to enable access to the COMDIV0 and COMDIV1 registers. Cleared by ...
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ADuC7060 UART Control Register 1 This 8-bit register controls the operation of the UART in conjunction with COMCON0. Name: COMCON1 Address: 0xFFFF0710 Default value: 0x00 Access: Read and write Table 88. COMCON1 MMR Bit Designations Bit Name Description 7:5 Reserved ...
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UART Status Register 1 COMSTA1 Register Name: COMSTA1 Address: 0xFFFF0718 Default value: 0x00 Access: Read only Function: COMSTA1 is a modem status register. Table 90. COMSTA1 MMR Bit Descriptions Bit Name Description 7:5 Reserved. Not used. 4 CTS Clear to ...
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ADuC7060 Table 92. COMIID0 MMR Bit Designations Status Bits[2:1] Bit 0 Priority Definition interrupt Receive line status interrupt Receive buffer full interrupt Transmit buffer empty interrupt 00 0 ...
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The ADuC7060 incorporates peripheral that can configured as a fully I C-compatible I C bus master device fully I C bus-compatible slave device. The two pins ...
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ADuC7060 SERIAL CLOCK GENERATION 2 The I C master in the system generates the serial clock for a transfer. The master channel can be configured to operate in fast mode (400 kHz) or standard mode (100 kHz). The bit rate ...
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Table 94. I2CMCON MMR Bit Designations Bit Name Description 15:9 Reserved. These bits are reserved and should not be written to I2CMCENI I C transmission complete interrupt enable bit. Set this bit to enable an interrupt on detecting ...
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ADuC7060 Master Status, I2CMSTA, Register Name: I2CMSTA Address: 0xFFFF0904 Default value: 0x0000 Access: Read only Function: This 16-bit MMR is the Table 95. I2CMSTA MMR Bit Designations Bit Name Description Reserved. These bits are ...
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I C Master Receive, I2CMRX, Register Name: I2CMRX Address: 0xFFFF0908 Default value: 0x00 Access: Read only Function: This 8-bit MMR is the I register Master Transmit, I2CMTX, Register Name: I2CMTX Address: 0xFFFF090C Default value: 0x00 Access: ...
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ADuC7060 Address 1, I2CADR1, Register Name: I2CADR1 Address: 0xFFFF091C Default value: 0x00 Access: Read and write Function: This 8-bit MMR is used in 10-bit addressing mode only. This register contains the least significant byte of the address. ...
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Table 101. I2CSCON MMR Bit Designations Bit Name Description Reserved bits. 10 I2CSTXENI Slave transmit interrupt enable bit. Set this bit to enable an interrupt after a slave transmits a byte. Clear this interrupt source. 9 I2CSRXENI ...
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ADuC7060 Slave Status, I2CSSTA, Register Name: I2CSSTA Address: 0xFFFF092C Default value: 0x0000 Access: Read and write Function: This 16-bit MMR is the I Table 102. I2CSSTA MMR Bit Designations Bit Name Description 15 Reserved bit. 14 I2CSTA ...
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Bit Name Description 2 3 I2CSRXQ I C slave receive request bit. This bit is set to 1 when the receive FIFO of the slave is not empty. This bit causes an interrupt to occur if the I2CSRXENI bit in ...
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ADuC7060 Common Registers FIFO Status, I2CFSTA, Register Name: I2CFSTA Address: 0xFFFF094C Default value: 0x0000 Access: Read and write Function: These 16-bit MMRs contain the status of the receive/transmit FIFOs in both master and slave ...
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SERIAL PERIPHERAL INTERFACE The ADuC7060 integrates a complete hardware serial peripheral interface (SPI) on-chip. SPI is an industry standard, synchronous serial interface that allows eight bits of data to be synchronously transmitted and simultaneously received, that is, full duplex up ...
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ADuC7060 SPI REGISTERS The following MMR registers control the SPI interface: SPISTA, SPIRX, SPITX, SPIDIV, and SPICON. SPI Status Register SPISTA Register Name: SPISTA Address: 0xFFFF0A00 Default value: 0x00000000 Access: Read only Function: This 32-bit MMR contains the status of ...
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SPIRX Register Name: SPIRX Address: 0xFFFF0A04 Default value: 0x00 Access: Read only Function: This 8-bit MMR is the SPI receive register. SPITX Register Name: SPITX Address: 0xFFFF0A08 Default value: 0x00 Access: Write only Function: This 8-bit MMR is the SPI ...
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ADuC7060 Table 105. SPICON MMR Bit Designations Bit Name Description SPIMDE SPI IRQ mode bits. These bits configure when the transmit/receive interrupts occur in a transfer. [00] = transmit interrupt occurs when 1 byte has been transferred. ...
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Bit Name Description 2 SPICPH Serial clock phase mode bit. Set by user, the serial clock pulses at the beginning of each serial bit transfer. Cleared by user, the serial clock pulses at the end of each serial bit transfer. ...
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ADuC7060 GENERAL-PURPOSE I/O The ADuC7060 features general-purpose bidirectional input/output (GPIO) pins. In general, many of the GPIO pins have multiple functions that are configurable by user code. By default, the GPIO pins are configured in GPIO mode. ...
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Table 108. GPxCON MMR Bit Descriptions Bit Description 31:30 Reserved. 29:28 Reserved. 27:26 Reserved. 25:24 Selects the function of the P0.6/RTS and P1.6/PWM pins. 23:22 Reserved. 21:20 Selects the function of the P0.5/CTS and P1.5/PWM3 pins. 19:18 Reserved. 17:16 Selects ...
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ADuC7060 GP0CON1 Control Registers The GP0CON1 write values are as follows: GP0KEY1 = 0x7, GP0CON1 = user value, and GP0KEY2 = 0x13. Name GP0KEY1 Address: 0xFFFF0464 Default value: 0xXXXX Access: Write only Function: When writing to GP0CON1, the value of ...
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HARDWARE DESIGN CONSIDERATIONS POWER SUPPLIES The ADuC7060 operational power supply voltage range is 2.375 V to 2.625 V. Separate analog and digital power supply pins (AVDD and DVDD, respectively) allow AVDD to be kept relatively free of noisy digital signals ...
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... ADuC7060BCPZ32-RL −40°C to +125°C 1 ADuC7060BSTZ32 −40°C to +125°C 1 ADuC7060BSTZ32-RL −40°C to +125°C 1 EVAL-ADuC7060QSPZ RoHS Compliant Part. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 0.60 MAX 0.60 MAX ...