KSZ8842-32MVLI Micrel Inc, KSZ8842-32MVLI Datasheet - Page 20

• Manufacturer Part Number: KSZ8842-32MVLI
• Description: 2-Port Ethernet Switch/Repeater + Generic (32-bit) Bus Interface( )
• Manufacturer: Micrel Inc

Specifications of KSZ8842-32MVLI

• Controller Type: Ethernet Switch Controller
• Interface: PCI
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Number Of Primary Switch Ports: 2
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog/Digital
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.5V
• Operating Supply Voltage (min): 3.1V
• Operating Temperature Classification: Industrial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1635 - BOARD EVALUATION KSZ8842-16MVL
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-3270

Micrel, Inc.
October 2007
Ball Number
G2
G1
G3
C3
A2
B2
A1
B1
C1
C2
D1
D2
H2
K1
K2
K3
H3
K4
H4
K5
H5
K6
H6
K7
F2
F1
J1
J2
J3
J4
J5
J6
Ball Name
PWRDN
TEST2
ADSN
RXM1
RXM2
RSTN
RXP1
TXM1
RXP2
TXM2
TXP1
TXP2
SWR
WRN
ISET
AEN
A13
A12
A10
A15
A14
A11
X1
X2
A9
A8
A7
A6
A5
A4
A3
A2
Type
Ipu
Ipd
Ipu
Ipd
Ipd
Ipu
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Ipu
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Ball Function
This ball can be pull-down for 8-bit bus mode, pull-up for 16-bit bus mode or
don’t care for 32-bit bus mode when EEEN is pull-down (without EEPROM).
Synchronous Write/Read
Write/Read signal for synchronous bus accesses. Write cycles when high and
Read cycles when low.
Address Enable
Address qualifier for the address decoding, active Low.
Write Strobe Not
Asynchronous write strobe, active Low.
Address Strobe Not
For systems that require address latching, the rising edge of ADSN indicates the
latching moment of A15-A1 and AEN.
Full-chip power-down. Low = Power down; High or floating = Normal operation.
Port 1 physical receive (MDI) or transmit (MDIX) signal (+ differential)
Port 1 physical receive (MDI) or transmit (MDIX) signal (– differential)
Port 1 physical transmit (MDI) or receive (MDIX) signal (+ differential)
Port 1 physical transmit (MDI) or receive (MDIX) signal (– differential)
Port 2 physical receive (MDI) or transmit (MDIX) signal (- differential)
Port 2 physical receive (MDI)or transmit (MDIX) signal (+ differential)
Port 2 physical transmit (MDI) or receive (MDIX) signal (- differential)
Port 2 physical transmit (MDI) or receive (MDIX) signal (+ differential)
Test input 2
For normal operation, left this ball open.
Set physical transmits output current.
Pull-down this ball with a 3.01K 1% resistor to ground.
25MHz crystal or oscillator clock connection.
Balls (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a 3.3V
tolerant oscillator and X2 is a no connect.
Note: Clock requirement is ± 50ppm for either crystal or oscillator.
Hardware reset ball (active Low). This reset input is required minimum of 10ms
low after stable supply voltage 3.3V.
Address 15
Address 14
Address 13
Address 12
Address 11
Address 10
Address 9
Address 8
Address 7
Address 6
Address 5
Address 4
Address 3
Address 2
20
KSZ8842-16/32 MQL/MVL/MVLI/MBL
M9999-102207-1.9