KSZ8842-PMBL AM Micrel Inc, KSZ8842-PMBL AM Datasheet - Page 20

• Manufacturer Part Number: KSZ8842-PMBL AM
• Description: 2-Port Ethernet Switch/Repeater + 32-bit/33MHz PCI Bus Interface( )
• Manufacturer: Micrel Inc

Specifications of KSZ8842-PMBL AM

• Controller Type: Ethernet Switch Controller
• Interface: PCI
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFBGA
• Number Of Primary Switch Ports: 2
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog/Digital
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.5V
• Operating Supply Voltage (min): 3.1V
• Operating Temperature Classification: Industrial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1636 - BOARD EVALUATION KSZ8842-PMQL
• Current - Supply: -
• Lead Free Status / RoHS Status: Supplier Unconfirmed, Lead free / RoHS Compliant
• Other names: 576-3348

Micrel, Inc.
KSZ8842-PMQL/PMBL
Functional Description
The KSZ8842-PMQL/PMBL contains one PCI interface unit, two 10/100 physical layer transceivers (PHYs), three MAC
units, and a RX/TX DMA channel all integrated with a Layer-2 switch.
Physical signal transmission and reception are enhanced through the use of analog circuits in the PHY that make the
design more efficient and allow for low power consumption.
Functional Overview: PCI Bus Interface Unit
PCI Bus Interface
The PCI Bus Interface implements PCI v2.2 bus protocols and configuration space. The KSZ8842-PMQL/PMBL
supports bus master reads and writes to CPU memory, and CPU access to on-chip register space. When the CPU
reads and writes the configuration registers of the KSZ8842-PMQL/PMBL, it is as a slave. So the KSZ8842-
PMQL/PMBL can be either a PCI bus master or slave. The PCI Bus Interface is also responsible for managing the DMA
interfaces and the host processors access. Arbitration logic within the PCI Bus Interface unit accepts bus requests from
the TXDMA logic and RXDMA logic.
The PCI bus interface also manages interrupt generation for a host processor.
TXDMA Logic and TX Buffer Manager
The KSZ8842-PMQL/PMBL supports a multi-frame, multi-fragment DMA gather process. Descriptors representing
frames are built and linked in system memory by a host processor. The TXDMA logic is responsible for transferring the
multi-fragment frame data from the host memory into the TX buffer.
The KSZ8842-PMQL/PMBL uses 4K bytes of transmit data buffer between the TXDMA logic and transmit MAC. When
the TXDMA logic determines there is enough space available in the TX buffer, the TXDMA logic will move any pending
frame data into the TX buffer. The management mechanism depends on the transmit descriptor list.
RXDMA Logic and RX Buffer Manager
The KSZ8842-PMQL/PMBL supports a multi-frame, multi-fragment DMA scatter process. Descriptors representing
frames are built and linked in system memory by the host processor. The RXDMA logic is responsible for transferring
the frame data from the RX buffer to the host memory.
The KSZ8842-PMQL/PMBL uses 4K bytes of receive data buffer between the receive MAC and RXDMA logic. The
management mechanism depends on the receive descriptor list.
Functional Overview: Physical Layer Transceiver (PHY)
100BASE-TX Transmit
The 100BASE-TX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI
conversion, and MLT3 encoding and transmission.
The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz serial
bit stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized
data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The output current is
set by an external1% 3.01KΩ resistor for the 1:1 transformer ratio.
The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude
balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output is also incorporated into the 100BASE-TX
transmitter.
100BASE-TX Receive
The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data
and clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial to parallel conversion.
The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted
pair cable. Since the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its
characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on
comparisons of incoming signal strength against some known cable characteristics, and then tunes itself for
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October 2007
M9999-100207-1.5