KSZ8842-PMBL AM Micrel Inc, KSZ8842-PMBL AM Datasheet - Page 39

• Manufacturer Part Number: KSZ8842-PMBL AM
• Description: 2-Port Ethernet Switch/Repeater + 32-bit/33MHz PCI Bus Interface( )
• Manufacturer: Micrel Inc

Specifications of KSZ8842-PMBL AM

• Controller Type: Ethernet Switch Controller
• Interface: PCI
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFBGA
• Number Of Primary Switch Ports: 2
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog/Digital
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.5V
• Operating Supply Voltage (min): 3.1V
• Operating Temperature Classification: Industrial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1636 - BOARD EVALUATION KSZ8842-PMQL
• Current - Supply: -
• Lead Free Status / RoHS Status: Supplier Unconfirmed, Lead free / RoHS Compliant
• Other names: 576-3348

Micrel, Inc.
The following table shows the TDES3 register bit fields.
PCI Configuration Registers
The KSZ8842-PMQL/PMBL implements 12 configuration registers. These registers are described in the following
subsections.
The KSZ8842-PMQL/PMBL enables a full software-driven initialization and configuration. This allows the software to
identify and query the KSZ8842-PMQL/PMBL. The KSZ8842-PMQL/PMBL treats configuration space write operations
to registers that are reserved as no-ops. That is, the access completes normally on the bus and the data is discarded.
Read accesses, to reserved or unimplemented registers, complete normally and a data value of 0 is returned.
Software reset has no effect on the configuration registers. Hardware reset sets the configuration registers to their
default values.
Configuration ID Register (CFID Offset 00H)
The CFID register identifies the KSZ8842-PMQL/PMBL. The following table shows the CFID register bit fields.
The following table shows the access rules of the register.
Command and Status Configuration Register (CFCS Offset 04H)
The CFCS register is divided into two sections: a command register (CFCS[15:0]) and a status register (CFCS[31:16]).
The command register provides control of the KSZ8842-PMQL/PMBL’s ability to generate and respond to PCI cycles.
When 0 is written to this register, the KSZ8842-PMQL/PMBL logically disconnects from the PCI bus for all accesses
except configuration accesses.
The status register records status information for the PCI bus-related events. The CFCS status bits are not cleared
when they are read. Writing 1 to these bits clears them; writing 0 has no effect.
October 2007
Category
Value after hardware reset
Write access rules
31 - 16
15 - 0
Configuration Register
Base Memory Address
Bit
Command and Status
31 - 0
Latency Timer
Subsystem ID
Bit
Identification
Reserved
Reserved
Reserved
Revision
Interrupt
Default
0x16C6
0x8842
Description
Next Descriptor Address
Indicates the physical memory address of the next descriptor in the descriptor ring.
The buffer address must be Word aligned.
Description
Device ID
Vendor ID
Specifies the manufacturer of the KSZ8842-PMQL/PMBL.
Identifier
CBMA
CFCS
CFRV
CFLT
CFID
CSID
CFIT
–
–
–
39
I/O Address Offset
Description
0x884216C6
Write has no effect on the KSZ8842-PMQL/PMBL.
40H-4CH
14H-28H
0CH
2CH
3CH
00H
04H
08H
10H
38H
0x884116C6
0x02000000
0x02000010
0x00000000
0x00000000
0x00000000
0x00000000
0x28140100
0x00000000
0x********
Default
KSZ8842-PMQL/PMBL
M9999-100207-1.5