DS21455 Maxim Integrated Products, DS21455 Datasheet - Page 127

• Manufacturer Part Number: DS21455
• Description: Network Controller & Processor ICs Quad E1-T1-J1 Single -Chip Transceiver (S
• Manufacturer: Maxim Integrated Products

Specifications of DS21455

• Product: Framer
• Number Of Transceivers: 4
• Data Rate: 64 Kbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 328 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: BGA

DS21455/DS21458 Quad T1/E1/J1 Transceivers
23. ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION (E1 ONLY)
The DS21455/DS21458, when operated in the E1 mode, provide for access to both the Sa and the Si bits
via three different methods. The first method is via a hardware scheme using the RLINK/RLCLK and
TLINK/TLCLK pins. The second method involves using the internal RAF/RNAF and TAF/TNAF
registers. The third method involves an expanded version of the second method.
23.1 Hardware Scheme (Method 1)
On the receive side, all of the received data is reported at the RLINK pin. Using the E1RCR2 register the
user can control the RLCLK pin to pulse during any combination of Sa bits. This allows the user to create
a clock that can be used to capture the needed Sa bits. If RSYNC is programmed to output a frame
boundary, it will identify the Si bits.
On the transmit side, the individual Sa bits can be either sourced from the internal TNAF register or
externally from the TLINK pin. Using the E1TCR2 register the framer can be programmed to source any
combination of the Sa bits from the TLINK pin. Si bits can be sampled through the TSER pin if by setting
E1TCR1.4 = 0.
23.2 Internal Register Scheme Based On Double-Frame (Method 2)
On the receive side, the RAF and RNAF registers will always report the data as it received in the Sa and
Si bit locations. The RAF and RNAF registers are updated on align frame boundaries. The setting of the
receive align frame bit in status register 4 (SR4.0) will indicate that the contents of the RAF and RNAF
have been updated. The host can use the SR4.0 bit to know when to read the RAF and RNAF registers.
The host has 250µs to retrieve the data before it is lost.
On the transmit side, data is sampled from the TAF and TNAF registers with the setting of the transmit
align frame bit in status register 4 (SR4.3). The host can use the SR4.3 bit to know when to update the
TAF and TNAF registers. It has 250µs to update the data or else the old data will be retransmitted. If the
TAF an TNAF registers are only being used to source the align frame and nonalign frame-sync
patterns, then the host need only write once to these registers. Data in the Si bit position will be
overwritten if the framer is programmed: (1) to source the Si bits from the TSER pin, (2) in the CRC-4
mode, or (3) with automatic E-bit insertion enabled. Data in the Sa bit position will be overwritten if any
of the E1TCR2.3 to E1TCR2.7 bits are set to one.
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