DS21455 Maxim Integrated Products, DS21455 Datasheet - Page 152

• Manufacturer Part Number: DS21455
• Description: Network Controller & Processor ICs Quad E1-T1-J1 Single -Chip Transceiver (S
• Manufacturer: Maxim Integrated Products

Specifications of DS21455

• Product: Framer
• Number Of Transceivers: 4
• Data Rate: 64 Kbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 328 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: BGA

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 2/Receive Packet Status (PS0 to PS2). These are real-time bits indicating the status as of the last read of the receive
FIFO.
Bit 3/Receive FIFO Empty (REMPTY). A real-time bit that is set high when the receive FIFO is empty.
Bit 4/Transmit FIFO Full (TFULL). A real-time bit that is set high when the FIFO is full.
Bit 5/Transmit FIFO Empty (TEMPTY). A real-time bit that is set high when the FIFO is empty.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/HDLC #1 Opening Byte Event (H1OBT). Set when the next byte available in the receive FIFO is the first byte of a
message.
Bit 1/HDLC #1 Transmit FIFO Underrun Event (H1UDR). Set when the transmit FIFO empties out without having seen
the TMEND bit set. An abort is automatically sent. This bit is latched and will be cleared when read.
Bit 2/HDLC #2 Opening Byte Event (H2OBT). Set when the next byte available in the receive FIFO is the first byte of a
message.
Bit 3/HDLC #2 Transmit FIFO Underrun Event (H2UDR). Set when the transmit FIFO empties out without having seen
the TMEND bit set. An abort is automatically sent. This bit is latched and will be cleared when read.
PS2
0
0
0
0
1
1
PS1
0
0
1
1
0
0
—
PS0
—
7
0
7
0
0
1
0
1
0
1
In Progress: End of message has not yet been reached.
Packet OK: Packet ended with correct CRC codeword.
CRC Error: A closing flag was detected, preceded by a corrupt CRC codeword.
Abort: Packet ended because an abort signal was detected (seven or more ones in a row).
Overrun: HDLC controller terminated reception of packet because receive FIFO is full.
Message Too Short: Three or fewer bytes including CRC.
—
6
0
INFO5, INFO6
HDLC #1 Information Register
HDLC #2 Information Register
2Eh, 2Fh
INFO4
HDLC Event Information Register #4
2Dh
—
6
0
TEMPTY
5
0
—
5
0
TFULL
4
0
—
4
0
PACKET STATUS
152 of 270
REMPTY
H2UDR
3
0
3
0
H2OBT
PS2
2
0
2
0
H1UDR
PS1
1
0
1
0
H1OBT
PS0
0
0
0
0