LAN91C110-PU SMSC, LAN91C110-PU Datasheet - Page 37

• Manufacturer Part Number: LAN91C110-PU
• Description: Ethernet ICs Non-PCI 10/100 Ethernet MAC
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN91C110-PU

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 5 V
• Supply Voltage (min): 0 V
• Supply Current (max): 40 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-144
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.2
SMSC LAN91C110 Rev. B
1 ISSUE ALLOCATE MEMORY FOR TX - N
2 WAIT FOR SUCCESSFUL COMPLETION
3 LOAD TRANSMIT DATA - Copy the TX packet
4 ISSUE "ENQUEUE PACKET NUMBER TO TX
5
6
7 a) SERVICE INTERRUPT - Read Interrupt Status
AEN=0
A3=0
A4-15 matches I/O BASE
BANK SELECT = 7
BANK SELECT = 4,5,6
Otherwise
Register. If it is a transmit interrupt, read the TX
FIFO Packet Number from the FIFO Ports
Register. Write the packet number into the Packet
Number Register. The corresponding status word
is now readable from memory. If status word
shows successful transmission, issue RELEASE
BYTES - the MMU attempts to allocate N bytes
of RAM.
CODE - Poll until the ALLOC INT bit is set or
enable its mask bit and wait for the interrupt.
The TX packet number is now at the Allocation
Result Register.
number into the Packet Number Register. Write
the Pointer Register, then use a block move
operation from the upper layer transmit queue
into the Data Register.
FIFO" - This command writes the number
present in the Packet Number Register into the
TX FIFO. The transmission is now enqueued.
No further CPU intervention is needed until a
transmit interrupt is generated.
Typical Flow of Events for Transmit (Auto Release = 0)
CYCLE
S/W DRIVER
Driven low. Transparently latched on
nADS rising edge.
High
High
DATASHEET
nCSOUT
Page 37
FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
The enqueued packet will be transferred to the
MAC block as a function of TXENA (nTCR) bit
and of the deferral process (1/2 duplex mode
only) state.
a) Upon transmit completion the first word in
memory is written with the status word. The
packet number is moved from the TX FIFO into
the TX completion FIFO. Interrupt is generated
by the TX completion FIFO being not empty.
b) If a TX failure occurs on any packets, TX INT
is generated and TXENA is cleared,
transmission sequence stops. The packet
number of the failure packet is presented at the
TX FIFO PORTS Register.
MAC SIDE
Ignored on writes.
Tri-stated on reads.
Ignore cycle.
Normal LAN91C110 cycle.
LAN91C110 DATA BUS
Revision 1.0 (11-04-08)
Datasheet