COM20020I-HT SMSC, COM20020I-HT Datasheet - Page 28

• Manufacturer Part Number: COM20020I-HT
• Description: Network Controller & Processor ICs ARCNET Contrllr
• Manufacturer: SMSC

Specifications of COM20020I-HT

• Product: Controller Area Network (CAN)
• Number Of Transceivers: 1
• Data Rate: 5 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Supply Current (max): 40 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SMSC COM20020I 3.3V Rev.E
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
BIT
6,5 (Reserved)
7
4
3
2
1
0
Receiver
Inhibited
Power On Reset
Test
Reconfiguration
Transmitter
Message
Acknowledged
Transmitter
Available
BIT NAME
SYMBOL
RECON
TEST
POR
TMA
TA
RI
Table 4 - STATUS REGISTER
This bit, if high, indicates that the receiver is not enabled because
either an "Enable Receive to Page fnn" command was never
issued, or a packet has been deposited into the RAM buffer page
fnn as specified by the last "Enable Receive to Page fnn"
command. No messages will be received until this command is
issued, and once the message has been received, the RI bit is set,
thereby inhibiting the receiver. The RI bit is cleared by issuing an
"Enable Receive to Page fnn" command. This bit, when set, will
cause an interrupt if the corresponding bit of the Interrupt Mask
Register (IMR) is also set. When this bit is set and another station
attempts to send a packet to this station, this station will send a
NAK.
These bits are undefined.
This bit, if high, indicates that the COM20020I 3V has been reset by
either a software reset, a hardware reset, or writing 00H to the
Node ID Register. The POR bit is cleared by the "Clear Flags"
command.
This bit is intended for test and diagnostic purposes. It is a logic
"0" under normal operating conditions.
This bit, if high, indicates that the Line Idle Timer has timed out
because the RXIN pin was idle for 41μS. The RECON bit is
cleared during a "Clear Flags" command. This bit, when set, will
cause an interrupt if the corresponding bit in the IMR is also set.
The interrupt service routine should consist of examining the
MYRECON bit of the Diagnostic Status Register to determine
whether there are consecutive reconfigurations caused by this
node.
This bit, if high, indicates that the packet transmitted as a result of
an "Enable Transmit from Page fnn" command has been
acknowledged. This bit should only be considered valid after the
TA bit (bit 0) is set. Broadcast messages are never acknowledged.
The TMA bit is cleared by issuing the "Enable Transmit from Page
fnn" command.
This bit, if high, indicates that the transmitter is available for
transmitting. This bit is set when the last byte of scheduled packet
has been transmitted out, or upon execution of a "Disable
Transmitter" command. The TA bit is cleared by issuing the
"Enable Transmit from Page fnn" command after the node next
receives the token. This bit, when set, will cause an interrupt if the
corresponding bit in the IMR is also set.
DATASHEET
Page 28
DESCRIPTION
Revision 09-11-06