COM20020I-HT SMSC, COM20020I-HT Datasheet - Page 31

• Manufacturer Part Number: COM20020I-HT
• Description: Network Controller & Processor ICs ARCNET Contrllr
• Manufacturer: SMSC

Specifications of COM20020I-HT

• Product: Controller Area Network (CAN)
• Number Of Transceivers: 1
• Data Rate: 5 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Supply Current (max): 40 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SMSC COM20020I 3.3V Rev.E
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
2,1,0
BIT
BIT
5-3
2-0
7-0
BIT
BIT
7-3
7
6
7
6
Read Data
Auto Increment
(Reserved)
Address 10-8
Address 7-0
Reserved
Sub Address 2,1,0
Reset
Command
Chaining Enable
BIT NAME
BIT NAME
BIT NAME
BIT NAME
RDDATA
AUTOINC
A10-A8
A7-A0
SUBAD
2,1,0
RESET
CCHEN
SYMBOL
SYMBOL
Table 8 - Address Pointer Low Register
SYMBOL
SYMBOL
Table 9 - SUB ADDRESS REGISTER
Table 10 - Configuration Register
These bits are undefined. They must be 0.
These bits determine which register at address 07 may be
accessed. The combinations are as follows:
SUBAD2
SUBAD1 and SUBAD0 are exactly the same as exist in the
Configuration Register. SUBAD2 is cleared automatically by
writing the Configuration Register.
A software reset of the COM20020I 3V is executed by writing
a logic "1" to this bit. A software reset does not reset the
microcontroller interface mode, nor does it affect the
Configuration Register. The only registers that the software
reset affect are the Status Register, the Next ID Register, and
the Diagnostic Status Register.
back to logic "0" to release the reset.
This bit, if high, enables the Command Chaining operation of
the device. Please refer to the Command Chaining section
for further details. A low level on this bit ensures software
compatibility with previous SMSC ARCNET devices.
DATASHEET
This bit tells the COM20020I 3V whether the following
access will be a read or write. A logic "1" prepares the
device for a read, a logic "0" prepares it for a write.
This bit controls whether the address pointer will increment
automatically.
increment of the pointer after each access, while a logic "0"
disables this function.
Access Memory section for further detail.
These bits are undefined. They must be 0.
These bits hold the upper three address bits which provide
addresses to RAM.
These bits hold the lower 8 address bits which provide the
addresses to RAM.
Page 31
0
0
0
0
1
1
1
1
SUBAD1 SUBAD0
A logic "1" on this bit allows automatic
0
0
1
1
0
0
1
1
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
Please refer to the Sequential
0
1
0
1
0
1
0
1
This bit must be brought
Register
Tentative ID (Same
Node ID
Setup 1
Next ID
Setup 2
Reserved
Reserved
Reserved
as in
Register)
Config
Revision 09-11-06