DS3141 Maxim Integrated Products, DS3141 Datasheet - Page 52

• Manufacturer Part Number: DS3141
• Description: Network Controller & Processor ICs Single Ch DS3;-E3 Fr Framer T3-E3 Framer
• Manufacturer: Maxim Integrated Products

Specifications of DS3141

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 2.048 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 90 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: CSBGA

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 31: BERT Bit Counter (BBC[31:0]). The BBCR registers are loaded with the value of the internal BERT
bit counter when the LC control bit in the
received. The bit counter starts counting when the BERT goes into receive synchronization (SYNC = 1) and
continues counting even if the BERT loses sync. The bit counter saturates and does not roll over. Upon saturation,
the BBCO status bit in the
registers and the internal bit counter is cleared. If the BERT is in sync when LC is toggled, the bit counter continues
to count up from zero. If the BERT is out of sync when LC is toggled, the bit counter is held at zero until the BERT
regains sync. The host processor should toggle LC after the BERT has synchronized and then toggle LC again
when the error-checking period is complete. If the framer loses synchronization during this period, then the
counting results are suspect.
BBC15
BBC23
BBC31
BBC7
7
0
7
0
7
0
7
0
BBC14
BBC22
BBC30
BSR
BBC6
6
0
6
0
6
0
6
0
register is set. When the LC bit is toggled, the bit count is loaded into the BBCR
BBCR1
BERT Bit Counter Register 1 (lower byte)
40h
BBCR2
BERT Bit Counter Register 2
41h
BBCR3
BERT Bit Counter Register 3
42h
BBCR4
BERT Bit Counter Register 4 (upper byte)
43h
BBC13
BBC21
BBC29
BBC5
BCR1
5
0
5
0
5
0
5
0
register is toggled. This 32-bit counter increments for each data bit
BBC12
BBC20
BBC28
52 of 88
BBC4
0
0
0
0
4
4
4
4
BBC11
BBC19
BBC27
BBC3
3
0
3
0
3
0
3
0
BBC10
BBC18
BBC26
BBC2
2
0
2
0
2
0
2
0
BBC17
BBC25
BBC1
BBC9
1
0
1
0
1
0
1
0
BBC16
BBC24
BBC0
BBC8
0
0
0
0
0
0
0
0